KR960010876B1 - Data translation parallel interface apparatus - Google Patents

Abstract

a central network transmitter retiming section (23) for retiming a transmission data of the central network (21); a local network receiver retiming section (24) for receiving the clock and data from the central network transmitter retiming section (23); a local network transmitter retiming section (25) for retiming a transmission data of the local network (22); a central network N bit serial/parallel converter (26) for converting serial data from the local network transmitter retiming section (25) into parallel data; and a central network receiver parallel/serial converter (27) for converting the N bit parallel data into serial data by use of the central network clock and block sync pulses.

Description

Parallel interface device for data transmission between central and local networks

1 is a block diagram of a conventional parallel interface device.

2 is a block diagram of a parallel interface device according to the present invention.

3 is a diagram illustrating a detailed configuration of a serial / parallel conversion unit of the central network receiver.

4 is a diagram illustrating a detailed configuration of a serial / parallel conversion unit of the central network receiver.

5 is a signal waveform diagram between main parts of the serial / parallel conversion means of FIG.

6 is a signal waveform diagram between main parts of the parallel / serial conversion means of FIG.

* Explanation of symbols for main parts of the drawings

11,21: Central network 12,22: Local network

13: central network transceiver retiming means 14: local network transceiver retiming means

23: central network transmitter retiming means 24: local network receiver retiming means

25: local network transmitter retiming means

26: central network receiver N-bit serial / parallel conversion means

27: N-bit parallel / serial conversion means of the central network receiver

311 to 31N, 321 to 32N: D flip flop

330: N counter

411 to 41N: D flip flop with multiplexer

420: N counter

DIN: Serial binary data transmitted by local network transmitter retiming means

DOUT1 to DOUTN, DIN1 to DINN: N-bit parallel data converted by serial / parallel means of central network receiver

DOUT: Serial data converted by parallel / serial means

LCP: Local network clock LBS: Local network block sync pulse

CCP: Central network clock CBS: Central network block sync pulse

The present invention compensates for the transmission inaccuracy of transmission data generated by various delay factors in the transmission of data between a central network having a clock source and a local network operated by a clock supplied from the central network. A parallel interface device for stably transmitting data.

1 is a configuration diagram of a conventional parallel interface device, 11 is a central network, 12 is a local network, 13 is a central network transmission and reception retiming device, 14 is a local network transmission and reception retiming device.

As shown in the drawing, the conventional parallel interface device uses the retiming device of each network without additional devices between the central network and the local network in parallel.

Therefore, in the prior art, when the distance between the local network and the central network is far apart and the distance between the central network and each local network is different, the transmission delay time of the data becomes inaccurate, so that data transmitted from the local network to the central network is transmitted. The higher the transmission bit rate of data, the more difficult it is to be stably in the central network.

The present invention devised to solve the above-mentioned problems is to compensate for the inaccuracy of the data transmission delay caused by various delay factors on the transmission path for the purpose of accurately retiming the data received from the local network in the central network. An object of the present invention is to provide a parallel interface device for data transmission between a central network and a local network that can stably receive data in a central network.

In order to achieve the above object, the present invention provides a parallel interface device for data transmission between a central network having a clock source and a local network operated by receiving a clock from the central network, wherein the transmission data of the central network is transmitted. A central network transmitter retiming means for retiming the network; A local network receiver retiming means for receiving clocks and data from the central network retiming means and retiming the received data to a reception clock; Local network transmitter retiming means for retiming the transmission data of the local network; Central network N-bit serial to extend the effective duration of data N times compared to existing data by converting received serial data into N-bit parallel data by receiving data, clock and block synchronization pulses from the local network transmitter retiming means Parallel conversion means; And a central network receiver parallel / serial conversion means connected to the central network N-bit serial / parallel means for serially converting the generated N-bit parallel data using a central network clock and block synchronization pulses. do.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, FIG. 2 is a functional block diagram of the present invention, where 21 is a central network, 22 is a local network, 23 is a central network transmitter retiming means, 24 is a local network receiver retiming means, and 25 is a local network transmitter retiming means , 26 denotes a central network receiver N-bit serial / parallel conversion means, and 27 denotes a central network receiver N-bit parallel / serial conversion means.

In FIG. 2, the central network 21 is a conventional network that performs a switching or transmission function. The central network 21 is connected to the local network 22 through a parallel interface device and typically performs a switching or transmission function in the center of the local network. When connected to the central network 21 through a parallel interface device to the network to perform a local exchange or transmission function. The central network transmitter retiming means 23 is a means for retiming data to be transmitted from the central network 21 to a clock of the central network and transmitting the same to the local network 22. The local network receiver retiming means 24 It is a means for retiming the data transmitted from the central network transmitter retiming means 23 to the local network clock and outputting the data to the local network 22. The local network transmitter retiming means 25 is a means for retiming the data to be transmitted in the local network 22 to a clock of the local network and transmitting the same to the central network 21. The central network receiver N-bit serial / parallel conversion means 26 converts the serial data received from the local network transmitter retiming means 25 together with the N-bit parallel data using the received local network clock and block synchronization pulse. Is a means for outputting to N-bit parallel / serial conversion means 27, which is composed of 2N D-flops and counters, and converts serial data into N-bit parallel data to extend the effective duration of the data by N times. do.

The central network receiver N-bit parallel / serial conversion means 27 converts the N-bit parallel data converted by the central network receiver N-bit serial / parallel conversion means 26 again by using the clock and block synchronization pulses of the central network. Means for converting into serial data and outputting to the central network 21. N D-flop flops with multiplexers. Effective persistence of data by the N-bit serial / parallel conversion means of the central network receiver. If the delayed time between the clock and block synchronization pulses received from the local network 22 and the central network clock and block synchronization pulses is within N times of the data period, the data having a time extended by N times is stably received. Convert to serial data.

3 is a detailed block diagram of the central network receiver serial / parallel means 26, where 311 to 31N each represent N D-flop flops for N-bit serial / parallel conversion, and 330 is a counter.

In the figure, the D-flop 311 inputs a clock (LCP) received from the local network to the clock input terminal, and the data received from the local network to the input terminal, respectively, and outputs the output to the D-flop 312 and 32N data input terminals. Input the output of flop 311 to the data input and the clock received from the local network to the clock input, respectively, and output its output as D-flop 311 to 31N i (i is any integer between 1 and N). Is the D-flop 31 (i + 1) and 32 (N-i) outputs to the input of data. Output them to the data input terminal of +1). The counter 330 starts counting at the rising transition of the clock received from the local network and the block sync pulse (LBS), and then outputs a logic level 0. Then, the rising transition of the clock received at the local network 22 occurs at an integer number of N. At each moment, a logic level 1 is generated for one period of the clock, and the output of the D-flop 31N is input to the data input terminal, and the output of the counter 330 is input to the clock input terminal, thereby rising to the output of the counter 330. Whenever a transition occurs, the data DOUT1 is outputted, and the D-flop flop 322 inputs the output of the D-flop 31 (N-1) to the data input terminal, and the data DOUT2 whenever the rising transition of the counter 330 occurs. Outputs That is, the i-th D-flop flop of D-flop 321 to 32N (i is any integer between 1 and N) inputs the output of the Ni- 1st D-flop flop of D-flop 311 to 31N into the data input terminal. Whenever the rising transition of the counter 330 occurs, the data DOUTi is output in such a manner that N parallel data DIN1, DIN2, ..., DIN (N-1), DINN are output.

4 is a detailed configuration diagram of the central network receiver parallel / serial conversion means 27. Reference numerals 411 to 41N denote D-flop flops having N multiplexers for parallel / serial conversion and 420 is a counter.

In the figure, the counter 420 inputs the block synchronization pulse CBS and the clock CPC of the central network to the inputs of the clear and clock of the counter, respectively, and starts counting at the transition of the central network block synchronization pulse and outputs logic level 0. The logic level 1 is output to the select terminal S of the D-flop 411 to 41N multiplexer having the multiplexer for a time corresponding to one cycle of the clock when the rising transition of the central network clock is an integer multiple of N.

The D-flop flop 411 having a multiplexer inputs the output of the counter 420 to the selection terminal S, and inputs the output data DIN1 of FIG. 3 and the output of the D-flop flop 412 having the multiplexer to the data input terminal, respectively. When the output of 420 is logic level 1, DIN1 is output to the central network at every rising transition of the central network clock. When the output of the counter 420 is logic level 0, the output of the D-flop flop 412 having a multiplexer is received as an input. After entering, whenever the rising transition of the clock of the central network occurs, it is output to the central network. The D-flop flop 412 having a multiplexer inputs the output of the counter 420 to the selection terminal S, and the output of the D-flop flop 413 having the multiplexer to the data input terminal, respectively. Whenever the rising transition of the central network clock (CCP) occurs, the output of the D-flop flop 413 with the far multiplexer occurs when the output of 420 is logic level 1, and when the output of counter 420 is logic level 0. Output to D-flop flop 411 with multiplexer. That is, the output of the D-flop flop 41 (i + 1) with the i-th multiplexer (i is any integer between 1 and N) is changed to the D-flop with data multiplexer whenever the clock transition of the central network occurs. The parallel data is converted back into serial data by outputting to 41 (i + 1) and output to DOUT.

The signal waveform diagram of each part of FIG. 3 is shown in FIG. 5. In FIG. 5, the block sync pulse LBB is generated at logic level 0 for a time corresponding to one period of the clock LCP for every data block. .

The signal waveform diagram of each part of FIG. 4 is shown in FIG. 6, in which the block sync pulse CCB is generated at logic level 0 for a time corresponding to one period of the clock CCC for every data block. .

In FIG. 3 and FIG. 4, the central network receiver N-bit serial / parallel conversion means 26 converts the data DIN transmitted from the local network transmitter retiming means 25 into N-bit parallel data DOUT1, DOUT2,... .., DOUT (N-1), DOUTN), so that the effective duration of the data is extended N times compared to the existing data (DIN), so that the transmission delay deviation between the local network and the central network is increased by N times When within the time, the central network receiver N-bit parallel / serial conversion means 27 can stably receive the data transmitted from the local network 22.

According to the present invention, a serial / parallel conversion means performed by the above processing is performed in a parallel interface receiver between a central network having a clock source and a local network operated by receiving clock and block synchronization pulses from the central network. By using a delay compensation circuit using a serial conversion means, it is possible to compensate for an incorrect transmission delay of data caused by various delay elements during transmission, so that even if the data received in the central network has an incorrect delay by various delay factors, If the block synchronization pulse of the central network exists only within the received data valid duration extended by N times by the serial / parallel conversion means, the data can be stably received by the clock of the central network.

Claims (3)

A parallel interface device for data transmission between a central network 21 having a clock source and a local network 22 operated by receiving a clock from the central network, wherein the transmission data of the central network 21 is transmitted. A central network transmitter retiming means (23) for retiming the network; A local network receiver retiming means (24) for receiving a clock and data from the central network retiming means (23) and retiming the received data to a reception clock; A local network transmitter retiming means (25) for retiming the transmission data of the local network (22); Receiving data, clock and block synchronization pulses from the local network transmitter retiming means 25, converting the serial data received into N-bit parallel data to extend the effective duration of the data N times compared to the existing data N-bit serial / parallel conversion means 26; And a central network receiver parallel / serial converting means 27 connected to the central network N-bit serial / parallel means and serially converting the generated N-bit parallel data using a central network clock and block synchronization pulses. Parallel interface device for data transmission between the central network and the local network. According to claim 1, The N-bit serial-to-parallel conversion means 26, D-flop flop receiving the clock received from the local network 22 side as a common clock is multi-dependently connected to each other, first However, at the input terminal of the D-flop flop 311, 1N D-flop flops 311 to 31N to which data received from the local network 22 side are input; A counter 330 for counting and outputting the rising transition of the clock LCP according to the block synchronization pulse LBS on the side of the local network 22; And receiving an i-th output of the first N D-flop flops 311 to 31N into a data input terminal of an N−i + 1 th D-flop flop. Parallel interface device for data transmission between the central network and the local network, characterized in that consisting of 2N D-flop flops (321 to 32N) for receiving a clock input of the output of the output. The counter of claim 2, wherein the central network receiver parallel / serial converting means (27) counts and outputs the rising transition of the clock (CCP) in accordance with the block synchronization pulse (CBS) on the central network (21). 420); The D-flop flops having multiplexers are connected in multiple stages by receiving the output of the counter 420 through the selection terminal S, and the second N D-flop flops 321 to 32N are connected to the input terminals of the respective D-flop flops. And a D flip flop (411 to 41N) having 3N multiplexers to which output data is input.