CN117879743A - FPGA-based optical communication ranging method and system - Google Patents

Abstract

The invention discloses an optical communication ranging method based on an FPGA, which comprises the following steps: acquiring coarse delay time through a parallel clock in the IP core; receiving original serial data through a shift register, and acquiring phase information of the serial data under a parallel clock according to the position of a ranging code detected in the shift register; correcting the coarse delay time according to the phase information to obtain corrected ranging time; and acquiring a ranging result based on the corrected ranging time. Under the condition of using an IP core, the invention acquires the phase information of the serial data under the parallel clock according to the position of the ranging code detected in the shift register, so that the data transmission delay can be controlled to be about 1serial clock precision no matter the communication rate is high or low, and the measurement precision is improved to 1serial clock from 1parallel clock which can only be achieved in the prior art.

Description

FPGA-based optical communication ranging method and system

Technical Field

The invention relates to the technical field of laser communication, in particular to an optical communication ranging method and system based on FPGA.

Background

In a space optical communication system, distance information of both communication parties is obtained in real time, and the method has important guiding significance for self-adaptive adjustment of transmission power control, receiving gain control and the like of both communication parties. The transmission delay of the data between the two devices can be obtained through cooperative communication of the two devices, so that the distance information is obtained. The method comprises the following specific steps: the transmitting end is at t ₀ Transmitting a specific K code (such as K28.0, K code is a comm code, which is a start and end mark of a frame or a control character for correcting and aligning a data stream) at a moment, wherein K in K28.0 refers to the comm code, a number between K and a decimal point refers to the last 5 bits of 8-bit data, a number behind the decimal point refers to the first 3 bits of 8-bit data, and a receiving end at t ₁ The K code is received at the moment and at t ₂ Time feedback transmits K code (K28.1), and the transmitting end transmits the K code at t ₃ And receiving the K code at any time, wherein the sending end and the receiving end both time the time difference of local sending and receiving, finally subtracting the time difference of the receiving end from the time difference of the sending end, and taking half of the time difference to obtain the time delay of unidirectional data transmission, and obtaining the distance information of the two parties by multiplying the data by the speed of light.

When the optical communication serial data rate is lower than 800Mbps (taking the highest output clock rate of an XC7K325T chip MMCM as an example), the signal is generally LVDS (Low Voltage Differential Signaling, namely a low-voltage differential signal; the theoretical rate of LVDS is more than 155Mbps, the recommended maximum rate is 655Mbps, the theoretical limit rate is 1.923Gbps, the maximum serial rate of LVDS in practical use is more than 622Mbps, the maximum serial rate of LVDS in an FPGA depends on the frequency multiplication rate of a crystal oscillator, and the maximum serial rate of LVDS in an FPGA is 800Mbps as an example), and the normal pin of the FPGA is accessed for receiving and transmitting LVDS data. At this time, a parallel data-to-serial data module can be written by oneself, the sequence of the corresponding K code is detected through a serial clock, the delay of K code transmission is obtained, and the accuracy of the delay measured by a single device can be controlled to be about 1 Tclk (1 serial clock).

When the optical communication serial data rate is higher than 500Mbps (taking XC7K325T chip GTX IP as an example, the transmission rate is 500 Mbps-10 Gbps, the CML level transmission rate is theoretically 2.5G-10 Gbps, but the rate interval of the IP inside the FPGA is 500 Mbps-10 Gbps), the signal is typically CML (Current Mode Logic, differential signal based on CMOS), PECL (Positive Emitter Coupled Logic, positive emitter coupling logic level), etc., the GTX IP core inside the FPGA (Intellectual Property Core, the IP core is defined in the semiconductor industry as "a pre-designed circuit function module for ASIC or FPGA". In short, the IP core is a predefined circuit function module ") can be used to implement high-speed data communication. However, the IP core only outputs parallel data (for example, when serial data is 1Gbps, the IP core outputs 40 bits@25m, the clock is 25M, the data bit width of one clock period is 40 bits, the rate is equivalent to 1Gbps, but the IP provides the user with 40 bits of data under a 25MHz clock), if the method is used for measuring, the time delay precision measured by a single device can only be controlled to be 1Tpclk (1 parallel clock). That is, when higher rate communication is performed, the accuracy is rather worse on the premise of using the IP core.

Disclosure of Invention

Aiming at least one defect or improvement requirement of the prior art, the invention provides an optical communication ranging method and system based on an FPGA, which are used for realizing the communication ranging function which can control the precision to be 1 Tclk and/or can support different communication rate switching conditions no matter what communication rate.

To achieve the above object, according to a first aspect of the present invention, there is provided an optical communication ranging method based on FPGA, including:

acquiring coarse delay time through a parallel clock in the IP core;

receiving original serial data through a shift register, and acquiring phase information of the serial data under a parallel clock according to the position of a ranging code detected in the shift register;

correcting the coarse delay time according to the phase information to obtain corrected ranging time;

and acquiring a ranging result based on the corrected ranging time.

Further, the obtaining the coarse delay time through the parallel clock inside the IP core includes:

the receiving end of the IP core sends t of the ranging code at the sending end ₀ Generating a start pulse by transmitting a data parallel clock at the same time at the moment, and giving the start pin of the time digital conversion chip;

the receiving end receives t detected by the data parallel clock when receiving the ranging code ₄ Generating an end pulse through the received data parallel clock at the moment, and giving an end pin of the time digital conversion chip;

wherein the coarse delay time is t _{Coarse size} ＝t ₄ －t ₀ 。

Further, the acquiring the phase information of the serial data under the parallel clock according to the position of the ranging code detected in the shift register includes:

if the ranging code detected in the shift register is just at the output of one serial clock, the arrival time of the ranging code is the current parallel clock time;

subtracting the time of N serial clocks on the basis of the coarse delay time if the first bit of the ranging code appears in the N last bit of the last serial data;

the phase information is the time of N serial clocks to be subtracted.

Further, the formula for correcting the coarse delay time according to the phase information to obtain the corrected ranging time includes:

Δt ₀ ＝(t _{coarse size} －Δt ₃ －Δt ₁ )/2；

Wherein t is _{Coarse size} For the coarse delay time, Δt ₃ For the phase information, Δt ₁ For the forwarding delay of the receiving end, delta t ₀ And correcting the ranging time.

Further, the formula for obtaining the ranging result based on the corrected ranging time includes:

s＝Δt ₀ ×v _{light source} ；

Wherein s is the ranging result, v _{Light source} Is the speed of light.

Further, the IP core adopts a GTX IP core of XILINX;

the method comprises the steps of setting a GTX IP core of XILINX to be start from scrach mode, selecting an 8B10B mode to be NONE, selecting a data bit width to be 20bit, not selecting an RX SLIDE mode, selecting a transmitting clock to be TXOUTCLK, and selecting a receiving clock to be RXOUTCLK, so as to ensure that the obtained FPGA serial data is original data which is not subjected to 8B10B encoding and decoding.

Further, the ranging code is sent in a gap between data packets of the original serial data, so as to avoid occupying the data bandwidth of the network port.

According to a second aspect of the present invention, there is also provided an optical communication ranging method based on FPGA, including:

transmitting a high-speed signal in a first speed range through a transmitting end of the IP core, and transmitting a low-speed signal in a second speed range through a transmitting end of the low-voltage differential signal interface;

selecting an adaptive signal between the received high-speed signal and low-speed signal through a cross point chip according to the current communication mode and sending the adaptive signal;

the selected adaptive signals are duplicated into two identical signals through a cross point chip and are respectively sent to a receiving end of the IP core and a receiving end of the low-voltage differential signal interface;

one of the two receiving ends can detect the correct ranging code sequence and judge the communication mode of the transmitting end;

the receiving end, which can detect the correct ranging code sequence, outputs a signal adapted to the communication mode of the transmitting end.

According to a third aspect of the present invention, there is provided an FPGA-based optical communication ranging system comprising:

the coarse delay time acquisition module is used for acquiring the coarse delay time through a parallel clock in the IP core;

the phase information acquisition module is used for acquiring phase information of the serial data under a parallel clock according to the position of the ranging code detected in the shift register;

the corrected ranging time acquisition module is used for correcting the coarse delay time according to the phase information so as to acquire corrected ranging time;

and the ranging result acquisition module is used for acquiring a ranging result based on the corrected ranging time.

According to a fourth aspect of the present invention, there is also provided an FPGA-based optical communication ranging system, comprising:

the IP core comprises a corresponding transmitting end and a corresponding receiving end and is used for receiving and transmitting high-speed signals in a first speed range;

the low-voltage differential signal interface also comprises a corresponding transmitting end and a corresponding receiving end, and is used for receiving and transmitting low-speed signals in a second speed range;

the cross point chip is used for selecting an adaptive signal between the received high-speed signal and the received low-speed signal according to the current communication mode and sending the adaptive signal out, and is also used for copying the selected adaptive signal into two identical signals and respectively sending the two identical signals to the receiving end of the IP core and the receiving end of the low-voltage differential signal interface;

one of the receiving end of the IP core and the receiving end of the low-voltage differential signal interface can detect a correct ranging code sequence and determine a communication mode of the transmitting end, and output a signal adapting to the communication mode of the transmitting end.

In general, the above technical solutions conceived by the present invention, compared with the prior art, enable the following beneficial effects to be obtained:

(1) Under the condition of using an IP core, the invention acquires the phase information of the serial data under the parallel clock according to the position of the ranging code detected in the shift register, so that the data transmission delay can be controlled to be about 1serial clock precision no matter the communication rate is high or low, and the measurement precision is improved to 1serial clock from 1parallel clock which can only be achieved in the prior art. If the serial-parallel conversion ratio of the high-speed signal is 40:1, the precision can be improved by 40 times, and the unidirectional measurement precision can reach 1ns when the theoretical communication rate is 1 Gbps.

(2) At present, ethernet data are transmitted in a communication mode, time gaps exist among data packets, and the invention is arranged to transmit ranging codes in the time gaps, so that the whole ranging process is completed in the time gaps of data transmission, the bandwidth of communication is not affected, and the integration of communication ranging is realized. The ranging can assist the communication equipment to realize the functions of transmitting power control, receiving gain control, high-precision time service and the like.

(3) The invention realizes multiplexing of the transmitted data through the cross point chip, simultaneously realizes copying and shunting of the received data, and recognizes real data rate information through different modules, thereby realizing the communication ranging integrated function under the premise of communication rate switching. On one hand, the invention realizes the communication compatibility of tens of Mbps to hundreds of Mbps low rate and 0.5 Gbps-10 Gbps high rate; on the other hand, multiplexing and splitting of the electric signals are adopted, multiplexing and splitting of the traditional optical paths are replaced, only one optical module is needed to transmit and receive data, the size of the equipment and the complexity of installation are reduced, the cost is saved, and the design is simplified.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a core flowchart of an optical communication ranging method based on an FPGA according to an embodiment of the present invention;

fig. 2 is a signal transceiving timing chart of an optical communication ranging method based on an FPGA according to an embodiment of the present invention;

fig. 3 is a schematic circuit structure diagram of an optical communication ranging system based on an FPGA according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.

The terms first, second, third and the like in the description, in the claims, or in the above-described figures, are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order. Furthermore, the terms "comprise" or "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed or inherent to such process, method, article, or apparatus but may alternatively include other steps or elements not listed or inherent to such process, method, article, or apparatus.

In the case where the communication rate is low, there is no problem in that the ranging accuracy is lowered with LVDS. When the communication rate is relatively high, a GTX IP core using an FPGA is generally selected, and only a parallel clock can be acquired in this case, which results in a great discount on the ranging accuracy. Based on the situation, the invention adopts a new technical idea, and the precision can be controlled to be 1 Tclk under the condition of using the IP core. The main technical idea is that original data received in series are obtained, the arrival time of the data is determined by finding the position of a special character K code, which is equivalent to obtaining the phase information of the serial data under a parallel clock, and the precision of 1 Tclk is achieved. Taking 1Gbps as an example, if the parallel clock is 25M, the data is 40 bits, the time of one parallel clock is equal to the time of 40 serial clocks, and if the received K code is just output by one serial clock, the moment when the K code arrives is the moment of the current parallel clock; if the first bit of the received K code is the last bit of the last data, the actual arrival time of the K code is equal to the time of the current parallel clock minus the time of one serial clock, namely the position information, namely the phase information, of the data, so that the actual arrival time of the data is determined.

Referring to fig. 1 and 2, in the first embodiment, setting XILINX (global leading programmable logic complete solution provider) GTX IP core as start from scrach mode, 8B10B mode as NONE, data bit width as 20bit, not hooking RX SLIDE mode, transmit clock as TXOUTCLK, receive clock as RXOUTCLK, this setting can ensure that the data of the acquired FPGA is the original data not 8B10B encoded.

The delay from transmitting K code to receiving K code includes two parts, one is delay information of parallel data of IP core and the other is phase information of parallel original data. After the chip is initialized, a start pulse and an end pulse are respectively given on two pins, and the chip can calculate Time information between the two pulses), so that the coarse delay Time can be measured. More specifically, t ₀ At the moment, the transmitting end of the IP core (actually the transmitting end of the IP core of the ranging initiator, hereinafter the same applies, abbreviated as transmitting end) transmits a K28.0 ranging code; t is t ₁ At the moment, the receiving end of the IP core (actually the receiving end of the IP core of the ranging initiator, hereinafter, abbreviated as receiving end) receives the K28.0 ranging code; t is t ₂ At this time, the receiving end sends the K28.1 feedback code, and then delays local forwarding (the receiving end receives K28.0 and sends the K28.1 back, this process is time-consuming and called forwarding delay) Δt ₁ Feedback feedA transmitting end; t is t ₃ At the moment, the transmitting end detects the K28.1 code. The time to be measured here is Δt ₀ (which is equal to Deltat ₂ The method comprises the following steps: the round-trip time for signal transmission between two targets should be equal). The receiving end of the IP core is at t ₀ Generating a start pulse to the start pin of the TDC chip by transmitting the data parallel clock TXCLK at time, at t ₄ Generating a pulse by receiving a data parallel clock RXCLK at the moment, feeding the pulse to a stop1 pin of the TDC chip, and reading a REG_0 register of the TDC to obtain a coarse delay time t _{Coarse size} ＝t ₄ －t ₀ 。

The specific method for acquiring the phase information is to send the received 20-bit data to a 40-bit shift register, detect the position of the K code in the register, and determine the accurate time information of the first bit of the K code. More specifically, based on the detected position of the K code in the shift register, for example, if the bit number [19:0 ] in the 40bit shift register]bit detects the K28.1 code and represents the phase information deltat ₃ =1 Tpclk, if [20:1 ] in the 40bit shift register]bit detects the K28.1 code and represents the phase information deltat ₃ =1tpclk+1tsclk. Because the clock of serial data can not be acquired in the FPGA, the initial pulse and the end pulse are given by the parallel clock in the IP core, and the coarse delay time is measured; the fine delay time is required to be corrected by the phase information on the basis of the coarse delay time. After the received data is sent to the shift register, the position of the K code is found in the shift register. If the received K code is just output by a serial clock, the moment of arrival of the K code is the moment of the current parallel clock; if the first bit of the K code appears at the last bit of the last serial data, subtracting the time of a serial clock on the basis of coarse delay; if the first bit of the K code occurs at the last digit of the serial data, the time of the two serial clocks needs to be subtracted on the basis of the coarse delay, and so on. The time of the serial clocks to be subtracted is the phase information delta t ₃ 。

After the measurement is finished, the known time of the transmitting end is t ₀ 、t ₄ And Deltat ₃ (the sender can obtain the accurate t ₀ Time t ₄ Time and Δt ₃ Time). Similarly, the receiving end can calculate the accurate delta t ₁ Time, and feeds back this time to the sender. Thus correcting the ranging time (fine delay time) Δt ₀ ＝(t ₄ －t ₀ －Δt ₃ －Δt ₁ )/2＝(t _{Coarse size} －Δt ₃ －Δt ₁ )/2。

The delay of the serial-parallel conversion time of the data (the process of sending the parallel data to the FPGA to the serial data output of the FPGA is delayed and can only be corrected as an error) is not considered here, because the serial-parallel conversion time inside the IP core can be found to be fixed in the actual measurement process. The fixed time delay can be calibrated into a systematic error by a certain means and subtracted in the actual ranging process.

The formula for obtaining the ranging result based on the corrected ranging time is: s=Δt ₀ ×v _{Light source} . Wherein s is the ranging result, v _{Light source} Is the speed of light. Electromagnetic waves such as signals propagate at the speed of light.

At present, the communication transmission is Ethernet data, time gaps are reserved among data packets, and the embodiment is set to send ranging codes in the time gaps, so that the whole ranging process is completed in the time gaps of the data transmission, the bandwidth of the communication is not affected, and the integration of communication ranging is realized. The ranging can assist the communication equipment to realize the functions of transmitting power control, receiving gain control, high-precision time service and the like.

Under the condition of using an IP core, the embodiment acquires the phase information of the serial data under the parallel clock according to the position of the ranging code detected in the shift register, so that the data transmission delay can be controlled to be about 1serial clock accuracy no matter the communication rate is high or low, and the measurement accuracy is improved to 1serial clock from 1parallel clock which can only be achieved in the prior art. If the serial-parallel conversion ratio of the high-speed signal is 40:1, the precision can be improved by 40 times, and the unidirectional measurement precision can reach 1ns when the theoretical communication rate is 1 Gbps.

In a second embodiment, there is provided an FPGA-based optical communication ranging system, including:

and the coarse delay time acquisition module is used for acquiring the coarse delay time through a parallel clock in the IP core.

And the phase information acquisition module is used for acquiring the phase information of the serial data under the parallel clock according to the position of the ranging code detected in the shift register.

And the corrected ranging time acquisition module is used for correcting the coarse delay time according to the phase information so as to acquire the corrected ranging time.

And the ranging result acquisition module is used for acquiring a ranging result based on the corrected ranging time.

The specific technical features and corresponding refinement features of each module unit may refer to the first embodiment, and will not be described herein.

If the device switches between different rates for communication, a function of ranging under the condition of different communication rates needs to be ensured. The invention provides a new technical idea, and the method meets the communication ranging integrated function under the premise of communication rate switching. The main technical idea is that a cross point chip is used for completing the copying and shunting process of data, signals are divided into two parts in the chip and sent to a processing module which is not communicated, and the communication rate switching function is realized.

In a third embodiment, an optical communication ranging method based on FPGA includes:

and transmitting the high-speed signal in the first speed range through a transmitting end of the IP core, and transmitting the low-speed signal in the second speed range through a transmitting end of the low-voltage differential signal interface. Wherein, the first speed range can be 10 Mbps-1.923 Gbps (the theoretical speed of LVDS is more than 155Mbps, the recommended maximum speed is 655Mbps, the theoretical limit speed is 1.923Gbps, the maximum serial speed of LVDS in the FPGA depends on the frequency doubling speed of crystal oscillator and is 800Mbps for example), and the second speed range can be 500 Mbps-10 Gbps.

According to the current communication mode, an adaptive signal is selected from the received high-speed signal and the received low-speed signal through the cross point chip and sent out.

The selected adaptive signals are duplicated into two identical signals through the cross point chip and are respectively sent to the receiving end of the IP core and the receiving end of the low-voltage differential signal interface.

One of the two receiving ends can detect the correct ranging code sequence and judge the communication mode of the transmitting end.

The receiving end, which can detect the correct ranging code sequence, outputs a signal adapted to the communication mode of the transmitting end.

The specific idea of this third embodiment can be seen in the corresponding hardware design of the fourth embodiment.

Referring to fig. 3, in the fourth embodiment, a high-speed signal is transmitted and received through a GTX IP (e.g., XILINX GTX IP core), and a low-speed signal is transmitted and received through an LVDS interface, and only one channel of data is used at the same time. The data of the two channels are selectively output through the 2X2 cross point chip (the 2X2 cross point chip has two input ends A, B and two output ends C, D, and can select the port A to output to the port C or select the port B to output to the port C, so that the data is selectively output). The receiving end receives the signal and copies and outputs the signal through the 2X2 cross chip (if the cross chip is used at the receiving end, the data of the port A is sent to C and D at the same time, the signal copying is realized on the circuit), the same signal copies into two identical data, the receiving port of the GTX IP and the receiving port of the LVDS interface are respectively driven, the data of the two ports respectively enter a high-speed data processing module and a low-speed rate processing module, and the transmitting end either transmits the high-speed signal or transmits the low-speed signal in a certain moment, and only one module at the receiving end can detect the correct K code sequence, so that the communication mode (the data transmitting rate) of the opposite party can be judged. For example, when the receiving rate is 100M or 1000M, the signals are sent to two data processing modules through the cross point chip, the module responsible for 100M data processing can detect the K code and then finish the subsequent data processing, and at this time, the module responsible for 1000M data processing cannot detect the K code, and the module does not work; while when the reception rate is 1000M, only the module responsible for 1000M data processing will work. The receiving end selects the data of the module which can work normally as output. In addition, the function of N1 selection can be realized in a cascading mode, and more different communication rates are supported.

The fourth embodiment realizes multiplexing of sending data through the cross point chip, copying and splitting of receiving data, and identifying real data rate information through different modules, and realizes the communication ranging integrated function under the premise of communication rate switching. On one hand, the communication compatibility between the low rate of tens of Mbps to hundreds of Mbps and the high rate of 0.5Gbps to 10Gbps is realized; on the other hand, multiplexing and splitting of the electric signals are adopted, multiplexing and splitting of the traditional optical paths are replaced, only one optical module is needed to transmit and receive data, the size of the equipment and the complexity of installation are reduced, the cost is saved, and the design is simplified.

Those skilled in the art will appreciate that the features recited in the various embodiments of the disclosure and/or in the claims may be combined in various combinations and/or combinations, even if such combinations or combinations are not explicitly recited in the disclosure. In particular, various combinations and/or combinations of the features recited in the various embodiments of the disclosure and/or the claims may be made without departing from the spirit and teachings of the disclosure, all of which fall within the scope of the disclosure.

While the present disclosure has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. The scope of the disclosure should, therefore, not be limited to the above-described embodiments, but should be determined not only by the following claims, but also by the equivalents of the following claims.

Claims (10)

1. An optical communication ranging method based on an FPGA is characterized by comprising the following steps:

acquiring coarse delay time through a parallel clock in the IP core;

receiving original serial data through a shift register, and acquiring phase information of the serial data under a parallel clock according to the position of a ranging code detected in the shift register;

correcting the coarse delay time according to the phase information to obtain corrected ranging time;

and acquiring a ranging result based on the corrected ranging time.

2. The FPGA-based optical communication ranging method of claim 1, wherein the obtaining the coarse delay time by the parallel clock inside the IP core comprises:

the receiving end of the IP core sends t of the ranging code at the sending end ₀ Generating a start pulse by transmitting a data parallel clock at the same time at the moment, and giving the start pin of the time digital conversion chip;

the receiving end receives t detected by the data parallel clock when receiving the ranging code ₄ Generating an end pulse through the received data parallel clock at the moment, and giving an end pin of the time digital conversion chip;

wherein the coarse delay time is t _{Coarse size} ＝t ₄ －t ₀ 。

3. The FPGA-based optical communication ranging method of claim 2, wherein the acquiring phase information of the serial data under the parallel clock according to the position of the ranging code detected in the shift register comprises:

if the ranging code detected in the shift register is just at the output of one serial clock, the arrival time of the ranging code is the current parallel clock time;

subtracting the time of N serial clocks on the basis of the coarse delay time if the first bit of the ranging code appears in the N last bit of the last serial data;

the phase information is the time of N serial clocks to be subtracted.

4. The FPGA-based optical communication ranging method of claim 3, wherein correcting the coarse delay time based on the phase information to obtain a formula for correcting the ranging time comprises:

Δt ₀ ＝(t _{coarse size} －Δt ₃ －Δt ₁ )/2；

Wherein t is _{Coarse size} For the coarse delay time, Δt ₃ For the phase information, Δt ₁ For the forwarding delay of the receiving end, delta t ₀ And correcting the ranging time.

5. The FPGA-based optical communication ranging method of claim 4, wherein the formula for obtaining a ranging result based on the corrected ranging time comprises:

s＝Δt ₀ ×v _{light source} ；

Wherein s is the ranging result, v _{Light source} Is the speed of light.

6. The FPGA-based optical communications ranging method of claim 1, wherein the IP core is a XILINX GTX IP core;

the method comprises the steps of setting a GTX IP core of XILINX to be start from scrach mode, selecting an 8B10B mode to be NONE, selecting a data bit width to be 20bit, not selecting an RX SLIDE mode, selecting a transmitting clock to be TXOUTCLK, and selecting a receiving clock to be RXOUTCLK, so as to ensure that the obtained FPGA serial data is original data which is not subjected to 8B10B encoding and decoding.

7. The FPGA-based optical communication ranging method of claim 1, wherein the ranging code is transmitted in a gap between data packets of original serial data to avoid occupying a data bandwidth of a portal.

8. An optical communication ranging method based on an FPGA is characterized by comprising the following steps:

transmitting a high-speed signal in a first speed range through a transmitting end of the IP core, and transmitting a low-speed signal in a second speed range through a transmitting end of the low-voltage differential signal interface;

selecting an adaptive signal between the received high-speed signal and low-speed signal through a cross point chip according to the current communication mode and sending the adaptive signal;

the selected adaptive signals are duplicated into two identical signals through a cross point chip and are respectively sent to a receiving end of the IP core and a receiving end of the low-voltage differential signal interface;

one of the two receiving ends can detect the correct ranging code sequence and judge the communication mode of the transmitting end;

the receiving end, which can detect the correct ranging code sequence, outputs a signal adapted to the communication mode of the transmitting end.

9. An FPGA-based optical communication ranging system, comprising:

the coarse delay time acquisition module is used for acquiring the coarse delay time through a parallel clock in the IP core;

the phase information acquisition module is used for acquiring phase information of the serial data under a parallel clock according to the position of the ranging code detected in the shift register;

the corrected ranging time acquisition module is used for correcting the coarse delay time according to the phase information so as to acquire corrected ranging time;

and the ranging result acquisition module is used for acquiring a ranging result based on the corrected ranging time.

10. An FPGA-based optical communication ranging system, comprising:

the IP core comprises a corresponding transmitting end and a corresponding receiving end and is used for receiving and transmitting high-speed signals in a first speed range;

the low-voltage differential signal interface also comprises a corresponding transmitting end and a corresponding receiving end, and is used for receiving and transmitting low-speed signals in a second speed range;

the cross point chip is used for selecting an adaptive signal between the received high-speed signal and the received low-speed signal according to the current communication mode and sending the adaptive signal out, and is also used for copying the selected adaptive signal into two identical signals and respectively sending the two identical signals to the receiving end of the IP core and the receiving end of the low-voltage differential signal interface;

one of the receiving end of the IP core and the receiving end of the low-voltage differential signal interface can detect a correct ranging code sequence and determine a communication mode of the transmitting end, and output a signal adapting to the communication mode of the transmitting end.