WO2009121421A1

WO2009121421A1 - Method and apparatus for transferring timing information between clock domains

Info

Publication number: WO2009121421A1
Application number: PCT/EP2008/055948
Authority: WO
Inventors: Sergio Lanzone; Vincenzo Volpe; Orazio Toscano
Original assignee: Telefonaktiebolaget Lm Ericsson (Publ)
Priority date: 2008-03-31
Filing date: 2008-05-15
Publication date: 2009-10-08

Abstract

A method of transferring timing information between two clock domains in a communications system. The method comprises formatting the timing information (315) received in a first clock domain (clk1, f1) into reflected binary code (330), sampling the reflected binary code into a second clock domain (clk2, fpn), and reformatting the reflected binary code into timing information (350) in the second clock domain.

Description

Method and Apparatus for Transferring Timing Information Between Clock

Domains

Field of the Invention

The present invention relates to transferring timing information between two clock domains, in particular although not exclusively, for use in transferring timing information associated with a synchronous communications network such as SDH across a packet switched network such as Ethernet.

Background of the Invention

A large amount of existing network and communications traffic is currently transported over synchronous time division multiplexed networks, using for example synchronous digital hierarchy (SDH) or Synchronous Optical Network (SONET) technologies at the physical layer. However, the deployment of next generation networks utilising packet switched technology such as Ethernet and asynchronous transport technology such as optical transport network (OTN) based wavelength division multiplexing (WDM), means that traffic may be transported across both synchronous and asynchronous networks. When a synchronous time division multiplexed (TDM) network is bridged by a packet switched network (PN), it is necessary to transport timing information relating to the TDM network across the packet switched network. This allows the timing of a TDM signal transported across the packet switched network to be recovered for subsequent regeneration and transmission of a TDM signal across the TDM network.

An ingress node between a synchronous TDM network and a packet switched network receives TDM signals such as SDH frames and packages these into packets for transmitting across the packet switched network. Typically a time stamp field is added to the packets and carries timing information from the TDM network; for example, a clock count associated with a particular SDH frame. This timing information is used by an egress node which receives the packet to regenerate the TDM signal using the correct timing for each recovered SDH frame. It is important that the timing information from the first clock domain (TDM network) is precisely transferred to the second clock domain (the packet switched network) in order to generate an accurate time stamp in the second clock domain for use in regenerating the synchronous signal at the egress node. The quality of clock signals recovered from a packet switched network are defined in the ITU-T G.8261 standard's jitter and wander limits.

Summary of the Invention

The present invention provides a method of transferring timing information between two clock domains in a communications system. The method comprises formatting the timing information received in a first clock domain into reflected binary code; for example, Gray code. The method further comprises sampling the reflected binary code into a second clock domain. In an embodiment the first clock domain corresponds to a synchronous TDM network, and the second clock domain corresponds to an asynchronous packet switched network. The method further comprises reformatting the reflected binary code into timing information in the second clock domain. In an embodiment the timing information is a time stamp which can be inserted into a packet for transmission across a packet switched network.

The present invention also provides a network node comprising a time stamp generator arranged to generate a first time stamp using a first clock signal, a formatting circuit arranged to format the first time stamp into reflected binary code, and a sampling circuit arranged to sample the reflected binary code into sampled reflected binary code using a second clock signal. The node may also comprise a reformatting circuit arranged to reformat the sampled reflected binary code into a second time stamp.

By formatting the time stamp into a reflected binary code such as Gray code before sampling into the second clock domain, any errors in the sampling process are significantly reduced. This is because reflected binary codes are arranged to increment by changing only one bit per increment. This means that if there is a register violation in the sampling process, due to a data change in the time stamp in the first clock domain at the same time as a clocking pulse in the second clock domain, then at most there can only be a single bit value error. This compares with using a standard binary format in which an increment can result in two or more bit changes in the time stamp potentially resulting in a large time stamp error. The time stamps are used to generate an average clock signal for a synchronous TDM network on the other side of the packet switched network. By reducing the error rate of the time stamps transferred into the packet switched network clock domain, this recovered average clocking signal has improved accuracy compared with known arrangements.

Brief Description of the Drawings

Embodiments will now be described with reference to the following drawings, by way of example only and without intending to be limiting, in which:

Figure 1 shows a communication system according to an embodiment;

Figure 2 is a schematic diagram illustrating circuits within an ingress node of the system of Figure 1 and which perform a timing information transfer between two clock domains according to an embodiment;

Figure 3 illustrates a process of transferring a time stamp from one clock domain to another according to an embodiment;

Figure 4 is a partial illustration of the registers of the formatting and sampling circuits of Figure 2;

Figure 5 illustrates the timing constraints for accurately sampling a data change at one of the sampling circuit registers of Figure 4;

Figure 6 illustrates register violations in the sampling circuits of figure 4; Figure 7 is a table showing the magnitude of errors resulting from register violations when using standard binary code for time stamp sampling;

Figure 8 is a table showing the magnitude of errors resulting from register violations when using Gray code format for time stamp sampling;

Figure 9 shows logic circuitry for converting a binary format time stamp into a Gray code format time stamp;

Figure 10 shows a logic circuit for reformatting a Gray code time stamp to a binary time stamp; and

Figure 11 illustrates a method of transferring timing information from a first clock domain to a second clock domain according to an embodiment.

Description of the Embodiments

Referring to figure 1 , a communication system according to an embodiment is shown. The communication system 100 comprises two incoming synchronous networks 105-1 and 105-2, which have their signals TDMl and TDM2 carried across a packet switched network 120 to subsequent synchronous networks 135-1 and 135-2. The synchronous signals TDMl and TDM2 may be based on SDH or SONET technology for example. The packet switched network 120 may be based on Ethernet over wavelength division multiplex (WDM) technology for example or a technology such as OTN over WDM.

The communication system 100 also comprises a first or ingress node 115 which couples the synchronous networks 105-1 and 105-2 to the packet switched or asynchronous network 120, and a second or egress node 130 which couples the packet switched network 120 to the outgoing synchronous networks 135-1 and 135-2. The synchronous networks 105-1 and 135-1 carrying a synchronous TDMl signal both operate synchronously at frequency fl. Synchronous networks 105-2 and 135-2 carrying another synchronous TDM2 signal both operate synchronously at frequency f2. The packet switched network 120 operates asynchronously at frequency fpn. In order to recover or regenerate the synchronous signals TDMl and TDM2 received by the ingress node 115, timing information about these synchronous signals must be transported across the asynchronous packet switched network 120 to the egress node 130. Typically this timing information is in the form of a time stamp generated using the incoming synchronous signals TDMl and TDM2 respectively. A clock signal is usually generated at the ingress node 115 using the received synchronous signal TDMl . This first clock signal operates at the frequency fl of the incoming synchronous signal TDMl which together form a first clock domain. Typically a counter counts the first clock signal pulses in order to generate a time stamp, which is associated with frames or parts of the received synchronous signal TDMl. The synchronous signal TDMl comprises a sequence of frames 110-1, and each frame may be associated with a time stamp by the ingress node 115. The received frames 110-1 may be inserted into respective packets 125 by the ingress node, which are then transmitted across the packet switched network 120 towards the egress node 130. A similar process occurs at the ingress node 115 for other received synchronous signals for example TDM2. The egress node 130 receives these packets 125 and reassembles the synchronous signals TDMl and TDM2 using the respective received frames 110-1 and 110-2.

In order to accurately and precisely regenerate the outgoing synchronous signals TDMl and TDM2, the egress node 130 uses the timing information associated with the incoming synchronous signals TDMl and TDM2 received by the ingress node 115. Thus, the egress node 130 receives time stamps from the ingress node 115 which are averaged and used to generate a clock signal having frequencies fl and £2 as appropriate for generating the respective outgoing synchronous signals TDMl and TDM2 for transmission over the outgoing synchronous networks 135-1 and 135-2 respectively. The frames 110-1 of the outgoing synchronous signals are also correctly aligned within the signal using their timing information as would be appreciated by those skilled in the art. The accuracy and precision of the timing information used is therefore reflected in the accuracy and precision of the regenerated synchronous signals. More accurate and precise timing information allows the egress node to regenerate a clock signal for the outgoing synchronous network whose mean value is closer to the desired or ideal clock signal (accuracy) and whose variance is also better (precision).

Because the clock frequency fpn of the intermediate packet switch network 120 is different from the clock frequencies of the incoming synchronous networks 105-l(fl) and 105-2(f2) as well as the outgoing synchronous networks 135-l(fl) and 135-2(f2), the timing information or time stamps must be transferred across three clock domains. The ingress node 115 transfers the timing information between a first clock domain associated with one of the incoming synchronous networks 105-1 and 105-2, into a second clock domain associated with the packet switched network 120. The egress node 130 uses the timing information in the second clock domain to generate a clock signal for one of the outgoing synchronous networks 135-1 or 135-2. The operation and structure of the egress node 130 will be familiar to those skilled in the art, and therefore it is not further described here.

The transfer of the timing information or time stamps from one of the synchronous network 105-1 or 105-2 clock domains (fl or f2) to the asynchronous packet switched network clock domain (fpn) is achieved by sampling the timing information or time stamp presented in the first clock domain (fl or f2) at the clock frequency of the second clock domain (fpn). This sampling process is subject to errors at the register level. In order to minimise these errors, the ingress node 115 formats the timing information or time stamp into reflected binary code before sampling, and reformats the reflected binary code into the original coding format, typically binary code, after sampling as illustrated in more detail in Figure 2.

Figure 2 shows a timing information clock domain transfer arrangement or function 200, within the ingress node 115, and which comprises a time stamp generator 205, coupled to a formatting circuit 210, coupled to a sampling circuit 215, coupled to a reformatting circuit 220, which in turn is coupled to a packet generation circuit 225. The time stamp generator operates in the first clock domain at the frequency fl of a received synchronous signal TDMl. The sampling circuit 215 and packet generation circuit 225 operate in a second clock domain at frequency fpn associated with the packet switched network 120. The formatting circuit 210 and the reformatting circuit 220 are typically unclocked logic circuits.

The time stamp generator 205 uses the first clock signal CLKl of the first clock domain to generate timing information in the first clock domain, typically in the form of a 32bit binary coded time stamp. This binary coded time stamp is applied to the formatting circuit 210 which formats this timing information reflected binary code. Reflected binary code such as Gray code represents decimal values in such a way that there is only a 1 bit difference between the reflected binary code representation of one decimal value or number, and a decimal number 1 value higher or lower. This compares with standard binary code representations of these same numbers which may differ by more than one bit. For example, the binary representation of the decimal number 1 is 001, and the Gray code representation of this number is also 001. However, the binary representation of the decimal number 2 is 010 which means that two bits have changed compared with the decimal number 1 (001). The Gray code representation of decimal number 2 is 011 where only one bit has changed (compared with 001). The following sequence of Gray code representations of decimal numbers 0 through 7 illustrate the principle of only altering one bit for each increment of decimal number value; 000, 001, 011, 010, 110, 111, 101, 100. The way in which this manner of representing the timing information reduces errors when transferring between clock domains is described in more detail below.

The output of the formatting circuit 210, the reflected binary code representation of the timing information or time stamp, is sampled by the sampling circuit 215 in the second clock domain, the sampling circuit is operated by a second clock signal CLK2 at the frequency fpn of the packet switched network 120. The sampled reflected binary code timing information is output to the reformatting circuit 220 where it is formatted back into a binary code time stamp for example. This binary code time stamp may then be used by the packet generation circuit 225 to insert into packets 125 or 127 for transmission to the egress node 130.

Figure 3 illustrates a method of transferring timing information between two clock domains in more detail. The ingress node 115 comprises a receiver 305 which receives a synchronous signal TDMl from a synchronous network 105-1 operating at frequency fl. From this received signal TDMl, the receiver 305 generates a first clock signal CLKl which is used to operate part of the ingress node as will be appreciated by those skilled in the art. The receiver also forwards data 360 received from the synchronous signal TDMl to the packet generation circuit 255. This data 360 may be the entire synchronous signal TDMl, or the payload of this signal as would be appreciated by those skilled in the art. The first clock signal CLKl is fed to a counter 310 which is used as a time stamp generator. The counter simply counts the clock pulses from the first clock signals CLKl and generates a binary coded time stamp based on the current value of the counter.

The binary coded time stamp 310 is shown here in decimal format for simplicity of explanation, however it will be appreciated that in practice this will typically be a 32 bit binary number. The binary coded time stamp 315 is converted to Gray code by a binary to Gray code formatting circuit 320 in order to generate a Gray code or reflected binary code time stamp 330. A sampling circuit 215 operating in a second clock domain samples the Gray code time stamp 330 using a second clock signal CLK2 in order to generate a sampled Gray code time stamp 340. The sampled Gray code time stamp 340 is reformatted into a binary code time stamp in the second clock domain 350 using a Gray code to binary reformatting circuit 345. This time stamp (350) in the second clock domain is used by the packet generation circuit 255 to insert into packet 355 to be transmitted across the packet network. Typically data 360 will also be inserted into these packets 355, however in alternative embodiments the time stamp 350 may be transmitted in packets independently of the data 360. In a further alternative arrangement, the conversion from sampled Gray or reflected binary code timestamp 340 to binary timestamp 350 may be performed at the egress node 130.

Figure 4 is a partial view at the register level of the counter, formatting and sampling circuits. For simplicity of explanation only four registers 405 A-D of the counter 310 are shown. Similarly only four registers 415A-D of the sampling circuit 215 are shown. Connecting these registers are logic devices shown generally as 41 OA-D of the binary to Gray code formatting circuit 320. As is known each register 405 A-D and 415A-D comprise a data input D, a data output Q and a clocking input (>). The data output (Q) of the counter registers 405 A-D correspond to the binary code time stamp 315 in the first clock domain, and the data input (D) of the sampling registers 415A-D correspond to the Gray code formatted time stamp 330; each register corresponding to 1 bit of the respective time stamp. It will also be noted that the counter registers 405 A-D are clocked using the first clock signal CLKl whereas the sampling registers 415A-D are clocked using the second clock signal CLK2. Register violations occur when a data input (D) changes at substantially the same time as a clocking signal (CLK2) is received. Under these circumstances, the output (Q) of the effected register 415A-D is unpredictable so that it may accurately reflect the data value at its input (D) or it may generate the opposite value and in doing so generate a register error. The probability of a register error in these circumstances is 50%.

Figure 5 illustrates the circumstances under which register violations occur in sampling circuit registers. If a data change (D) occurs within a set up period Tsu before the clock signal pulse CLK2, or within a hold period Th thereafter, then a register violation occurs and the output (Q) of the register is unpredictable, typically there is a 50% chance of a register violation resulting in a register error - the output (Q) does not represent the input (D), for example D=I and Q=O. Because the circuit paths of each register 415A-D are different, the path length of the clocking signal CLK2 and the respective data signals (D) will typically be different for each register. Therefore the timing of the clocking signal CLK2 and the data signal (D) will be slightly different for each register 415A-D. This is indicated by the delay components δi_4 of the respective sample registers 415A-D. Therefore the occurrence of register violations over different clock cycles will typically be different for different registers.

Set up and hold register violations are illustrated in Figure 6 which shows the clock signal CLKl of the counter registers 405 A-D, together with the individual clock signals (CKL2) as received by the respective sample registers 415A-D. The clock signal CLK2 is shown with respective delays δ_1-4. For simplicity, corresponding clock signal delays are not shown at the counter registers (CLKl). It can be seen that set up or hold violations occur at different sampling circuit registers 415A-D at different times.

Figure 7 is a table illustrating the consequences of register errors in the sample registers 415A-D. As noted previously, a register error will occur typically 50% of the time in which a register violation (set up or hold) occurs. Column 1 shows the first clock signal CLKl cycle, column 2 shows the time stamp or counter decimal value, column 3 shows the corresponding binary value, column 4 indicates register errors, column 5 shows the results of those errors on the output binary value, and the last column shows the decimal value of the output binary values. Whilst register errors will not occur on every clock cycle, for the purposes of illustration and explanation, register errors have been shown on each clock cycle of the table. It can be seen that the sampled time stamp (column 6) can be considerably different from the input time stamp (column 7). For example, in clock 1 cycle 1, the time stamp value is 0 (decimal), whereas the sampled time stamp value is 5. Another error can be seen in clock cycle 2, where the input time stamp value is 1 and the sample time stamp value is 0. The time stamp value of clock cycle 5 is 4, whereas the sampled time stamp is 0. In clock cycle 5, the binary value is 0100=4 and there is a register error at register 2. The previous value of bit 2 was 0 (from clock cycle 4) and the new value of bit 2 is 1 (from 0100 in clock cycle 5). In other words this bit 2 has changed from 0 to 1 and as there is a register error a register violation has occurred in the sampled value (0000 = 0). More generally it can be seen that significant time stamp errors can occur, which results in inaccurate timing information being sent from the ingress node to the egress node. This in turn results in timing errors in the generation of a synchronous signal (TDMl or TD M2) on the subsequent synchronous networks 135-1 and 135-2.

Figure 8 shows a table similar to that of figure 7, but in which the binary time stamp values have been converted to Gray code before sampling. Thus column 4 shows the Gray code value of the binary time stamp value from column 3. Similarly, column 7 shows the binary value of the sampled Gray code time stamp of column 6. Column 6 shows the sampled Gray code time stamp value following sampling of a Gray code time stamp from column 4 with the same register errors from figure 7 shown in column 5. Referring to the decimal values of the input and sampled time stamps from columns 2 and 8 respectively, it can be seen that where errors occur, they are much smaller than those shown in figure 7. the errors are only one decimal value different, which compares favourably with the known arrangement demonstrated in figure 7 and in which differences of decimal value 5 can be seen. Thus the sample time stamps of the embodiments using Gray code or other reflected binary codes are significantly more accurate than those sampled using binary coded time stamps.

Figure 9 shows a simple logic circuit for converting the binary coded time stamp from the counter to the Gray code equivalent to be presented to the sampling circuit. The circuit uses an arrangement of XOR gates 910A as shown. For simplicity only 4 bits are shown, however it will be appreciated that this circuit could be extended to any number of bits for the time stamp. Figure 10 shows a corresponding circuit for reformatting the sampled time stamp from Gray code back to binary code. Again this circuit uses simple XOR gates 920A.

These simple formatting and reformatting circuits have reduced circuit complexity (gate counts), reduced latency, and better power dissipation compared with known arrangements for sampling time stamps or other timing information between clock domains. For example the embodiment compares favourably with arrangements using mirror registers to hold the data from one clock domain whilst being read into another clock domain. However this involves extra registers and also latency or delay of the time stamp into the second clock domain. Various other circuit arrangements based on persistency and validation checks of the data, or sampling the data using a higher clock frequency can alternatively be used, however these also require complex circuits. By contrast the present embodiments provide a simple solution which introduces no delay as the formatting and reformatting circuits are not clocked. Similarly these simple logic gates do not require significant power and are simple and cost effective to implement in hardware.

Figure 11 illustrates a method of transferring timing information between two clock domains in a communications network node. The method may be implemented in software or hardware within an ingress node coupling a synchronous network to an asynchronous packet switched network. The ingress node received a synchronous communication signal in a first clock domain at step 1105. For example an SDH signal TDMl operating at a clock rate having frequency fl is received. The node generates a first clock signal CLKl from the received signal at step 1110. The first clock signal CLKl may be derived using phase locked loops or other techniques that will be well known to those skilled in the art. The node generates timing information using the first clock signal at step 1115. Typically the timing information will be a binary time stamp generated by a counter receiving the generated clock signal as an input; however other methods may be used. The node then formats the timing information into reflected binary code at step 1120. This may be implemented using logic gates which convert a binary code time stamp into a Gray code time stamp. The node then samples the reflected binary code into a second clock domain at step 1125. As previously described, this may be implemented using registers clocked using a second clock signal CLK2. The node then reformats the reflected binary code into timing information in the second clock domain at step 1130. This may be implemented using simple logic gates to convert a sampled Gray code time stamp into a sampled binary code time stamp. The node inserts the timing information into a packet at step 1135. A packet generation circuit may insert the sampled binary time stamp into a packet together with data from the received synchronous signal at step 1140. Finally, the node transmits the packet including timing information onto the packet switched network at step 1145. This timing information in the second clock domain is received by an egress node coupled to the packet switched or asynchronous network. This timing information can then be used to generate a synchronous signal corresponding to the synchronous signal received by the ingress node. Because the timing information in the second clock domain is more accurate, the regenerated synchronous signal is also more accurate.

The various embodiments may be implemented in hardware or software as appropriate, for example as application specific integrated circuits (ASIC) or processor code executed on a processor. One or more embodiments have been described, however alterations and modifications which would be obvious to those skilled in the art are intended to be incorporated within the scope of the appended claims.

Claims

1. A method of transferring timing information between two clock domains in a communications system, the method comprising: formatting the timing information received in a first clock domain into reflected binary code; sampling the reflected binary code into a second clock domain; reformatting the reflected binary code into timing information in the second clock domain.

2. A method according to claim 1, wherein the reflected binary code is Gray code and the timing information is a binary timestamp.

3. A method according to claim 1 or 2, wherein the timing information in the first clock domain is derived from a synchronous communications signal received at a first node.

4. A method according to claim 3, further comprises re-generating the synchronous signal at a second node using the timing information in the second clock domain.

5. A method according to any one preceding claim, wherein the timing information in the second clock domain is inserted into a packet and sent over a packet switched network.

6. A method according to claim 5, wherein data from a communications signal in the first clock domain is also inserted into the packet.

7. A method according to any one preceding claim, wherein the method is performed in a network node coupling a synchronous network to an asynchronous network.

8. A network node comprising: a timestamp generator arranged to generate a first timestamp using a first clock signal; a formatting circuit arranged to format the first timestamp into reflected binary code; a sampling circuit arranged to sample the reflected binary code into a sampled reflected binary code using a second clock signal.

9. A network node according to claim 8, further comprising a reformatting circuit arranged to reformat the sampled reflected binary code into a second timestamp.

10. A network node according to claim 8 or 9, wherein the timestamp generator is a counter arranged to generate a binary first timestamp, and the reflected binary code is Gray code.

11. A network node according to any one of claims 8 to 10, further comprising a receiver arranged to receive a synchronous signal and to derive the first clock signal from said synchronous signal.

12. A network node according to any one of claims 8 to 11, further comprising a packet generation circuit arranged to insert the second timestamp into a packet for transmission over a packet switched network.

13. A network node according to claim 12, wherein the packet generation circuit is further arranged to insert data into the packet, the data received from a synchronous signal received by the network node.

14. A network node according to any one of claims 8 to 13, wherein the formatting and reformatting circuits comprise non-clocked binary logic gates connected directly to clocked registers of the respective timestamp generator and sampling circuit.

15. A network comprising a network node according to any one of claims 8 to 14, further comprising a second node arranged to generate a synchronous signal using the timing information in the second clock domain. .

16. A carrier medium carrying processor code which when executed on a processor is arranged to carry out the method of any one of claims 1 to 7.