KR100202943B1 - A system for transmitting the multiple-valued logic data - Google Patents

Abstract

In the present invention, multivalued logic signals from a binary coded system are converted to multivalued logic, thereby reducing complexity of input and output circuits and internal wiring, and increasing data processing speed. In the transmission system, when the binary logic data is input from the binary logic system, the first, second and third comparison means 10 for outputting a comparison signal for the binary logic data in comparison with the set reference value signal (10, 11, 12); First, second, and third signal generating means (15, 16, 17) for outputting predetermined multi-valued logic data to the system clock input from the system controller by the comparison signal from the comparison means (10, 11, 12). ; First to sixth delay elements 20 to 25 for performing respective time delays on the multivalued logic data from the first, second and third signal generating means 15, 16 and 17; An orifice 26 for outputting a predetermined output signal by multi-valued logic data signals from said first, second and third signal generating means (15, 16, 17); The synchronizing signal output means 27 which transmits a synchronizing signal to the multi-value logic data receiving system 51 by the output signal from the oragate 26 is characterized by the above-mentioned.

Description

A system for transmitting the multiple-valued logic data

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multivalued logical data transmission system, and in particular, by converting and transferring binary logic data from a system based on binary encoding into multivalued logic data, the complexity of input / output circuit and internal wiring is reduced, and data The present invention relates to a multi-valued logical data transmission system that can increase the processing speed.

FIG. 1 is a view schematically illustrating a concept of a general binary logic data transmission system, in which a predetermined decimal data, for example, 1025, is transmitted from a binary logic data transmission system to a binary logic data reception system. As described above, the data bus between the binary logical data transfer systems requires 11 data lines. In addition, when several types of modules are connected to the data line, the circuit between the binary logic data transmission and reception systems becomes more complicated.

As described above, when data is transmitted using binary logic between conventional binary logic transmission systems, input / output circuits and internal wiring become complicated, and data processing functions and processing speeds for a certain area are deteriorated. There was a problem.

Accordingly, the present invention has been made to solve the above-mentioned problems, and by converting binary logic data from a system based on binary coding into multivalued logical data, the complexity of input / output circuits and internal wiring is reduced, and data It is an object of the present invention to provide a multi-value logical data transmission system that can speed up processing.

The present invention for achieving the above object, the first, second and second outputting the comparison signal for the binary logic data when the binary logic data is input from the binary logic system, compared with the set reference signal Third comparing means; First, second and third signal generating means for outputting predetermined multi-valued logic data to the system clock input from the system control section by the comparison signal from the comparing means; First to sixth delay elements for performing respective time delays on the multivalued logic data from the first, second and third signal generating means; An orifice for outputting a predetermined output signal by the multivalued logic data signal from said first, second and third signal generating means; And a synchronizing signal output means for transmitting the synchronizing signal to the multi-value logical data receiving system by the output signal from the oragate.

According to the present invention configured as described above, by converting binary logic data from a system based on binary coding into multivalued logical data, the complexity of the input / output circuit and internal wiring is reduced, and the data processing speed is increased. It becomes possible.

1 is a view schematically showing a concept of a general binary logic data transmission system;

2 is a diagram schematically illustrating a concept of a multi-valued logical data transmission system;

3 is a detailed block diagram of a multi-value logical data transmission system according to the present invention;

4 is a view showing an operation waveform for explaining the operation of the multi-value logical data transmission system according to the present invention.

* Explanation of symbols for main parts of the drawings

10,11,12: first, second and third comparators

15, 16, 17: first, second and third signal generator

20 to 25: first to sixth delay elements 26: oragate,

27: synchronization signal output section 50: multi-value logical data transmission system

51: multi-value logical data reception system 100: binary data transmission system

101: binary logic data receiving system

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

On the other hand, multiple-valued logic is a current binary digital integrated circuit in such a manner that a digital system is constructed from an algorithm based on multivalued coding for a current binary digital system, such as an information system based on binary coding. It is possible to realize new hardware that overcomes the limitations.

Therefore, multi-value logic can increase the integration density and reduce the complexity of internal wiring while reducing the complexity of input and output. In addition, the complexity of the hardware can be reduced by increasing the data processing function and the storage density of a certain area, and by reducing the number of modules of the system hardware amount while facilitating mutual conversion with external signals.

Further, the processing time can be increased by reducing the number of steps of serial connection and the number of repetitions of operations, and the practical use of a quaternary mask ROM having such a feature, a dynamic RAM, a 32-bit multiplier, and the like are continuously studied. In addition, if there is general use with current binary logic, high speed and chip area can be reduced, and mixed with binary logic by multi-valued logic operation without modification of existing circuit that is composed of binary system. Done.

On the other hand, multivalued logic is an extension of the binary logic that is widely used in all fields of information and communication systems, and the binary circuit recognizes and processes only logic 0 and logic 1 according to high and low voltage or current flow. In multi-valued logic, the circuit processes various logic values, such as 0, 1, 2, or 3, depending on the magnitude of the voltage, the strength of the current, and the amount of charge.

The multi-value logic circuit can be divided into a voltage mode in which information is expressed in magnitude and polarity of a voltage, and a current mode in which information is expressed in magnitude and direction of a current, and a charge mode in which information is expressed by an amount of charge.

2 is a diagram schematically illustrating the concept of a multi-valued logical data transmission system. First, the multi-valued logic in the present embodiment will be described with reference to 16-valued logic. Therefore, in the case where it is desired to transfer predetermined data, for example, data corresponding to a number of 1025, from the 16-value logical data transmission system to the 16-value logical data reception system, as shown in FIG. Only two data lines are needed.

As described above, in the case of transferring data using the 16-value logic between the 16-value logic data transmission systems, the input / output circuit and the internal wiring are simple as described above, and the data processing function and processing speed for a certain area are improved. Will be.

3 is a detailed block diagram of a multi-valued logical data transmission system according to the present invention, wherein the multi-valued logic data transmission system includes first, second and third comparators 10, 11, and 12; First, second, and third signal generators (15, 16, 17); First to sixth delay elements 20 to 25; Oagate 26 and; The synchronization signal output section 27 is configured.

Meanwhile, when a predetermined binary signal of nine binary signals is input to the first, second, and third comparators 10, 11, and 12, respectively, the first, second, and third comparators 10, 11, 12 are provided. ) Compares the set reference signal with the input binary signal and matches the set signal to the first, second and third signal generators 15, 16 and 17, respectively. Will print.

The first, second, and third signal generators 15, 16, and 17 are system controllers (not shown) by comparison signals from the first, second, and third comparators 10, 11, and 12. For the system clock input from), data of predetermined multi-valued logic, for example, data of 16-valued logic, is output.

Thereafter, the 16-value logic data from the first signal generator 15 is transmitted to the multi-value logic data receiving system 51 through the first and second delay elements 20 and 21, and the second signal generator 16 16-value logic data from the third signal is transmitted to the multi-value logic data receiving system 51 through the third and fourth delay elements 22 and 23, and the 16-value logic data from the third signal generator 17 is generated. The fifth and sixth delay elements 24 and 25 are transmitted to the multivalued logic data receiving system 51. Here, the first to sixth delay elements 20 to 25 generate a time delay for each of the 16-value logic data from the respective first, second and third signal generators 15, 16 and 17. Let's go.

When the output signals from the first, second and third signal generators 15, 16, and 17 are input to the synchronization signal output unit 27 through the oragate 26, the synchronization signal output unit 27 ) Transmits the synchronization signal to the multi-valued logic data receiving system 51 by the output signal. Thereafter, the multi-value logical data receiving system 51 receives the synchronization signal and the 16-value logic data from the multi-value logical data transmission system 50 and converts the binary data into binary data.

4 is an operation waveform diagram for explaining the operation of the multi-value logical data transmission system according to the present invention. In this case, when data is to be transmitted in 16-value logic, one data is transmitted per 16 system clocks. Therefore, when the data of the predetermined decimal number, for example, 1025, is to be transmitted, the first, second and third signal generators 15, 16, 16) 16-value logical data 104 for the decimal data 1025 is outputted from the multi-valued logical data receiving system 51 through each data line.

Thereafter, the multi-value logic data receiving system 51 receives the synchronization signal and the 16-value logic data from the multi-value logic data receiving system 50 and converts the binary data into binary data. In this manner, when the binary logic data is converted into 16-value logic data and transmitted, only one synchronization signal line and three 16-value logic data lines are required, thereby reducing the data lines.

On the other hand, the reference numerals written in the components of the claims of the present application to facilitate the understanding of the present invention, and are not written in the intention to limit the technical scope of the present invention to the embodiments shown in the drawings. Further, various modifications can be made without departing from the scope of the invention.

As described above, according to the present invention, by converting binary logic data from a system based on binary coding into multivalued logical data, the complexity of the input / output circuit and internal wiring is reduced, and the data processing speed is increased. It can be speeded up.

Claims (6)

First, second, and third comparing means (10, 11, 12) for outputting a comparison signal for the corresponding binary logic data when the binary logic data is input from the binary logic system; First, second, and third signal generating means (15, 16, 17) for outputting predetermined multi-valued logic data to the system clock input from the system controller by the comparison signal from the comparison means (10, 11, 12). ; First to sixth delay elements 20 to 25 for performing respective time delays on the multivalued logic data from the first, second and third signal generating means 15, 16 and 17; An orifice 26 for outputting a predetermined output signal by multi-valued logic data signals from said first, second and third signal generating means (15, 16, 17); A multivalued logic data transmission system, comprising: synchronization signal output means (27) for transmitting a synchronization signal to the multivalued logic data reception system (51) by an output signal from the oragate (26). 2. The first and second delay elements (20, 21) according to claim 1, delay the multivalued logic data from the first signal generating means (15), and the third and fourth delay elements (22, 23). ) Delays the multi-valued logic data from the second signal generating means 16, and the fifth and sixth delay elements 24 and 25 delay the multi-valued logic data from the third signal generating means 17. A multi-value logical data transmission system, characterized in that The multi-value logical data transmission system according to claim 1, wherein the multi-value logical data transmission system converts binary logic data into 16-value logical data and transmits the converted binary data. 4. The multivalued logical data transmission system of claim 3, wherein the multivalued logical data transmission system transmits one data per 16 clocks. The method of claim 1, wherein the synchronization signal output means 27 of the first, second and third signal generator 16 (15, 16, 17) ^0, 16 ^1, 16 through the Iowa gate 26 ² A multi-valued logic data transmission system characterized by outputting a synchronous signal of one clock when digit data is input. 2. The multivalued logical data transmission system as claimed in claim 1, wherein said delay elements (20-25) comprise D flip flops.