RU2006102662A - Способ кодирования кода разреженного контроля четности - Google Patents
Способ кодирования кода разреженного контроля четности Download PDFInfo
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- RU2006102662A RU2006102662A RU2006102662/09A RU2006102662A RU2006102662A RU 2006102662 A RU2006102662 A RU 2006102662A RU 2006102662/09 A RU2006102662/09 A RU 2006102662/09A RU 2006102662 A RU2006102662 A RU 2006102662A RU 2006102662 A RU2006102662 A RU 2006102662A
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- 238000000034 method Methods 0.000 title claims 13
- 239000011159 matrix material Substances 0.000 claims 22
- 125000004122 cyclic group Chemical group 0.000 claims 4
- 238000006073 displacement reaction Methods 0.000 claims 3
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1191—Codes on graphs other than LDPC codes
- H03M13/1194—Repeat-accumulate [RA] codes
- H03M13/1197—Irregular repeat-accumulate [IRA] codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
- H03M13/1114—Merged schedule message passing algorithm with storage of sums of check-to-bit node messages or sums of bit-to-check node messages, e.g. in order to increase the memory efficiency
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1162—Array based LDPC codes, e.g. array codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
- H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/611—Specific encoding aspects, e.g. encoding by means of decoding
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
- H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
Claims (9)
1. Способ генерирования кода разреженного контроля четности, состоящего из матрицы информационной части и матрицы части четности, при этом способ содержит этапы, на которых изменяют матрицу информационной части на структуру кода массива и назначают последовательность степеней каждому из столбцов подматрицы; расширяют матрицу части четности таким образом, чтобы значение смещения между диагональными линиями имело заранее определенное значение в обобщенной двухдиагональной матрице, которая является матрицей части четности; повышают обобщенную двухдиагональную матрицу; определяют значение смещения для циклического сдвига столбцов в каждой подматрице повышенной обобщенной двухдиагональной матрицы; и выполняют процесс кодирования для определения символа четности, соответствующего столбцу матрицы части четности.
2. Способ по п.1, в котором последовательность степеней формируется в соответствии с уравнением (37)
3. Способ по п.1, в котором значение смещения между диагональными линиями является взаимнопростым в отношении числа столбцов в обобщенной двухдиагональной матрице.
4. Способ по п.1, в котором число строк в подматрице является простым числом.
5. Способ по п.1, в котором разность между суммой значений смещения для циклического сдвига строк подматрицы на диагональной линии в обобщенной двухдиагональной матрице, которая является матрицей части четности, и суммой значений смещения для циклического сдвига строк подматрицы на диагональной линии смещения не равна 0.
6. Способ по п.1, в котором процесс кодирования содержит этапы, на которых
(a) определяют символ четности первой строки в подматрице с индексом 0 столбца подматрицы на диагональной линии матрицы части четности;
(b) задают индекс строки в подматрице символа четности, идентичного определенному символу четности в индексе столбца в подматрице в подматрице на диагональной линии смещения, имеющей такой же индекс столбца подматрицы, что и индекс столбца подматрицы заданного символа четности;
(c) определяют символ четности, имеющий такой же индекс строки в заданной подматрице в подматрице на диагональной линии, имеющей такой же индекс строки подматрицы, что и индекс строки подматрицы на диагональной линии смещения; и
(d) многократно выполняют этапы (b) и (c) до тех пор, пока создание матрицы четности не будет завершено.
7. Способ по п.6, в котором на этапе (a) символ четности определяется суммой информационных символов матрицы информационной части, существующих в той же строке, что и индекс строки в подматрице, символы четности которой определяются.
8. Способ по п.6, в котором на этапе (b) индекс строки в подматрице задается в соответствии с уравнением (38)
где означает индекс строки в подматрице с индексом i столбца подматрицы на диагональной линии смещения, x(l) i означает индекс столбца в подматрице с индексом i столбца, существующем на диагональной линии, а означает значения смешения для циклического сдвига столбцов подматрицы с индексом i столбца подматрицы на диагональной линии смещения.
9. Способ по п.6, в котором на этапе (c) символ четности определяется в соответствии с уравнением (39):
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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KR1020030071456A KR100922956B1 (ko) | 2003-10-14 | 2003-10-14 | 저밀도 패리티 검사 코드의 부호화 방법 |
KR10-2003-0071456 | 2003-10-14 |
Publications (2)
Publication Number | Publication Date |
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RU2006102662A true RU2006102662A (ru) | 2006-06-27 |
RU2308803C2 RU2308803C2 (ru) | 2007-10-20 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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RU2006102662/09A RU2308803C2 (ru) | 2003-10-14 | 2004-10-14 | Способ кодирования кода разреженного контроля четности |
Country Status (9)
Country | Link |
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US (1) | US7458009B2 (ru) |
EP (1) | EP1673870B1 (ru) |
JP (1) | JP4199279B2 (ru) |
KR (1) | KR100922956B1 (ru) |
CN (1) | CN1830149B (ru) |
AU (1) | AU2004306640B9 (ru) |
DE (1) | DE602004016194D1 (ru) |
RU (1) | RU2308803C2 (ru) |
WO (1) | WO2005036758A1 (ru) |
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JP3808769B2 (ja) | 2001-12-27 | 2006-08-16 | 三菱電機株式会社 | Ldpc符号用検査行列生成方法 |
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CA2516716C (en) | 2003-02-26 | 2012-08-14 | Flarion Technologies, Inc. | Method and apparatus for performing low-density parity-check (ldpc) code operations using a multi-level permutation |
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AU2004306640A1 (en) | 2005-04-21 |
JP4199279B2 (ja) | 2008-12-17 |
EP1673870A1 (en) | 2006-06-28 |
KR100922956B1 (ko) | 2009-10-22 |
DE602004016194D1 (de) | 2008-10-09 |
US20070022354A1 (en) | 2007-01-25 |
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