RU1836687C - Device for time-division multiplexing of requests for writing and reading - Google Patents

Description

but the permissible frequency of requests to write and read. This is explained as follows.

We denote the possible delay of the buffer memory, for which the device in question generates control signals of the operating modes, through the RAM.

Then from the timing diagram of the prototype, it can be seen that the duration of the pulses of its synchronization g should be longer than the TZU, and the frequency f, synchronization should be:

1

 .

2t

In other words, to separate in time the simultaneously received write and read requests, the prototype needs a time of at least 2 tons, where TZU. The minimum period of receipt of write or read requests by the prototype should be longer than this time of 2 g by the value of the expectation of the synchronization pulse front, since only on the edge (leading or trailing) of this pulse will the execution of the first request begin. Obviously, the maximum possible waiting time for the leading or trailing edge of the synchronization pulse is equal to r. From all this it follows that the prototype device can only work if the expressions are satisfied:

(1)

(2)

t GZU (3)

where Tzap is the minimum possible period for requests to write data in the memory buffer; Here, is the minimum possible period for requests to read data from the buffer memory.

Thus, the speed of the information sources and receivers used with the prototype should be more than 3 times lower than the speed of the used buffer memory.

This circumstance significantly narrows the scope of effective applications of the prototype device.

In view of this, an object of the invention is to expand the scope of the device to separate time between write and read requests by reducing the criticality of the performance requirements of data sources and receivers.

The goal is achieved in that in a device for dividing time requests for writing and reading data containing RS read and write triggers, JK read and write triggers, T-trigger. moreover

the dividing frequency input of the device is connected to the T-input of the T-flip-flop, the output of which is connected to the clock inputs of the J "write and read triggers, the read and write request inputs are S-inputs of the RS-read and write triggers, direct JK outputs the read and write triggers are connected to the R-inputs of the corresponding RS-read and write triggers,

0

and also, respectively, with the read and write control outputs of the device, the K-inputs of the JK read and write triggers are connected to the zero potential of the device, an additional counter, an OR element,

5 first, second, and third AND elements, and the direct outputs of the JK read and write triggers are connected correspondingly to the first 1 l by the second inputs of the OR element, whose output s and the input of the dividing frequency of the device are connected respectively to the first and second inputs of the third AND element, the output of which connected to the counter input of the counter, the output of the counter is connected to the asynchronous R-inputs of the JK read and write triggers, the outputs of the RS read and write triggers are connected respectively to the first inputs of the first and second AND elements, the outputs of which are connected inens respectively with J-inputs of JK-read and write triggers,

The 0 inverse outputs of the JK triggers for writing and reading are connected respectively to the second inputs of the first and second elements I. The essence of the invention is to expand the scope of the device

5 to separate in time the requests for writing and reading data by reducing the criticality of the requirements for maximum speed of the interfaced sources and receivers of information sending requests for writing and reading data to the buffer memory, respectively.

Reducing the criticality of the requirements for maximum performance of data sources and receivers consists in

5 reducing the minimum possible period of receipt of write requests (Tzap) and reading (Tcht) of data in the buffer memory. This is achieved by significantly reducing the waiting time in

0 of the proposed device of the edge of the synchronization pulse, according to which the control signal of the operating mode of the buffer memory will begin to form.

To this end, the synchronization frequency fn

5 compared to the prototype device

increases k times: fw kf; gi Ј.

Correspondingly, the maximum waiting time for the start of service of the first of the simultaneously received read and write requests from the fifth device is reduced by a factor of k. This time becomes equal to -g.

In order for the memory mode control signal to be generated at the time t of the GEM, a special counter of synchronization pulses is introduced. This counter, after k synchronization pulses, after the device starts generating the control signal for the operating mode of the buffer memory, is full and initiates the end of the device generating this signal. After this device, the next request for use by the buffer memory is also transferred to the service and generates another control signal for its operation mode.

The described organization of operation of the device allows to reduce by 30% with respect to the prototype the minimum period of receipt of write requests (Tzap) and reading (TCH) of data in the buffer memory. This is the reason for a significant decrease in the criticality of the requirements for maximum performance of the working data sources and receivers working with the proposed device.

The introduction of the counter and its connections made it possible to determine the time at which the request for accessing the buffer memory was completed.

The introduction of the first and second AND elements and their connections made it possible to block the execution of subsequent requests for the use of a buffer memory until the service of the executed request is completed.

The introduction of the OR element and its connections made it possible to determine the moment of the beginning of the execution of the next request for access to the buffer memory and to generate the corresponding signal.

The introduction of the third element And and its connections made it possible to isolate those synchronization pulses of the device that entered it during the formation of a zero signal for controlling the operating mode of the buffer memory.

Fig. 1 is a functional block diagram of a device for dividing data write and read requests in time; figure 2 shows a temporary diagram of the operation of the device.

The device (figure 1) contains: RS-reader 1 reading, RS-2 reading trigger, JK-reading 3 reader, JK-recording 4 trigger, T-trigger 5, counter 6, element OR 7, first 8 .second 9, third 10 elements AND, inputs of 11 requests "and reading, 12 write requests, 13 dividing frequencies, outputs 14 of the read control, 15 write control,

The input 13 of the separation frequency is connected to the T-input of the T-trigger 5, the output of which

connected to the synchro-passages of the K-flip-flops 3 and 4, the inputs of 11,12 devices are respectively the S-inputs of the RS-flip-flops 1.2; the direct outputs of the JK flip-flops 3.4 are connected to the 5 R-inputs of the corresponding RS-flip-flops 1,2, and also respectively to the control outputs of reading 14 and writing 15 of the device, the K-inputs of the JK-triggers 3,4 are connected to the zero potential of the device, my

0 outputs of J K-triggers 3 of reading and 4 of writing are connected respectively to the first and second inputs of the OR element 7, the output of which is the vt input of the dividing frequency 13 of the device connected respectively to

5 by the first and second inputs of the third element And 10, the output of which is connected to the counting input of the counter b, the output of the counter 6 is connected to the asynchronous R-inputs of the JK read triggers and 4 records, the RS0 outputs of the 1 read and 2 write triggers are connected respectively to the first the inputs of the first 8 and second 9 AND elements, the outputs of which are connected respectively to the J-inputs of JK read triggers and 4 records, inverse 5 outputs of J K-triggers 3 records and 4 reads are connected respectively to the second inputs of AND elements 8.9.

The numbering adopted in FIG. 1 corresponds to the numbering adopted in FIG. 2,

0 Consider the functional purpose of the elements and and their connections in the proposed device (Fig. 1).

RS read asynchronous triggers 1 and 2 for storing single request signals for reading and writing data from a buffer memory, respectively. These signals are stored in the respective triggers 1 and 2 until the end of the execution of the corresponding requests.

Synchronous JK flip-flops with 3 reads and 4 records are designed to store and issue into the RAM memory of the source interface buffering device and

5 receiver of data of respective operation mode control signals (read / write) of this buffer RAM. The zero K-inputs of these triggers are connected to the mass of the device, i.e. they constantly have a zero signal level. JK triggers 3,4 have asynchronous R-BXOs set to zero. When a single overflow pulse is received at these inputs, the counter 6 of the JK trigger5 of the 3.4 ger is reset. The JK trigger of recording 3 goes over to a single state at a single signal at its J input along the leading edge of the signal at its sync input. The JK trigger 4 steps into a single state with a single signal at its J input along the trailing edge of the signal at its sync input.

The T-flip-flop 5 is designed to convert the dividing frequency from the input 13 of the device into a sequence of clock pulses, the leading edges of which synchronize the reading JK-trigger Z, and the rear edges -JK-trigger 4 recordings. The T-flip-flop 5 changes its state for the opposite at all times along the trailing edge of the pulses of the dividing frequency f from the input 13 of the device (see Fig. 2).

The OR element 7, the third AND 10, the counter 6 are intended to determine the end of the time the device will execute the next request for the use of the buffer memory. Counter b runs continuously in counting mode and increases its content by a unit every time along the trailing edge of the pulse from the output of element 10. 10. The output of counter 6 is its overflow output. A single pulse of short duration at the output of the counter 6 sets to the initial (zero) state J K-triggers

3 and 4. The conversion factor of the counter 6 k is chosen to be minimal, based on the satisfaction of the expression:

k then GZU (4)

T.O. each k-th pulse from the output of the And 10 element resets the counter 6 (restores) and, on its trailing edge, a short pulse is generated at the output of the counter 6, leading to the initial (zero) state J K-triggers 3 of the record and

4 readings. Figure 2 shows the timing diagram of the operation of the counter 6 with a conversion factor k 4.

The first element And 8 is designed to block the receipt of a read request signal from the output of the RS trigger 1 to the J input of the JK trigger 3 when the device is servicing a write request. In this case, the JK write trigger 4 is in a single state, and a zero signal is generated at its inverse output, prohibiting the passage of a single read request signal to the J input of trigger 3.

The second element And 9 is intended to block the receipt of the write request signal from the output of RS-Tpnrrepa 2 to the J-input of the JK trigger 4 when the device reads the request. The second element And 9 works similarly to the first element And 8,

The dividing frequency f at the input 13 of the device is a sequence of short pulses with a repetition period equal to one.

-iТ at

The larger the ratio. the less

There may be a time interval Tzap (Tht) between adjacent request signals

writing (reading). (See figure 2 and the evaluation section of the feasibility study).

Consider the operation of the proposed device when pairing the source and receiver of data,

0 In the initial state of the axis, the elements are in the zero state. The input 13 of the device receives pulses of the separation frequency synchronization (see figure 2). Element And 10 blocks their passage to

5 is the counter counter input 6. The T-trigger 5, along the: bottom edge of each synchronization pulse, switches sequentially from zero to a single state. The signals from its output are fed to the sync inputs JK0 of triggers 3 and 4 on J and K inputs of which there are zero signals. The device is in this state until 11 or 12 requests for reading or writing are received at its input.

5 Let the first pulse to the input 12 from the information source be a single pulse of the request signal for writing the data word to the buffer memory for subsequent transmission to the receiver of information. In this case, the RS-trig0 ger 2 goes into a single state. Element And 9 is open, because at its first input there is a single signal from the inverse output of the JK-trigger Z. From the output element. And 9 unit signal goes to J-input

5 of flip-flop 4. On the trailing edge of the next clock pulse from the output of T-flip-flop 5, the JK-flip-flop 4 transfers to a single state. At the output 15 of the device, a single control signal for writing data words from the information source to the buffer memory appears.

The signal from the output of the JK trigger 4 nullifies the RS trigger 2 and, through the OR element 7, opens the And 10 element for synchronization pulses. Counter 6 starts counting the time by which the JK trigger 4 generates a buffer control write signal. (Note that, after writing 4 units to the JK trigger, entering a request to read data at input 11 in the lead 0 only leads to its storage in RS trigger 1. JK trigger 3 remains in the zero state, because it The J-input is blocked by the And 8 element at the second input of which there is a zero-fifth signal from the inverse output of the JK trigger 4). On the trailing edge of the k-ro pulse from the output of the And 10 element, c4ef4HK 6 is zeroed and forms a single overflow pulse at its output, which is fed to the R-input of the JK triggers 3 and 4.

JK trigger 4 is zeroed, element And 8 is opened to pass the read request signal from trigger 1 to the J input of trigger 3. If there is no read request yet and RS trigger 1 is in the zero state, then on the leading edge of the next the clock signal from the output of the T-flip-flop 5 JK-flip-flop 3 will remain in the zero state. After this point, the device may receive the next write request. If such a request is received, the RS flip-flop 2 again switches to a single state, and then the cycle of the device generating the control signal for writing to the buffer memory is repeated. Otherwise, the device is waiting for the next request, being in the initial state,

Serving the device a request for reading data received at the input 11 of the device is similar to the described device servicing a write request.

Note that in order to ensure that at the moment of receiving the corresponding requests on the S-inputs of the RS-flip-flops 1 and 2, at the R-inputs of a single signal was not guaranteed, the choice of Tzap and Tht must satisfy the expressions:

Tzap 2k ro;. (5)

Tht 2k TO. (6)

When these inequalities are satisfied, the device allows the simultaneous requests to use the shared memory to be allocated for the time necessary for servicing.

Let us consider in detail the operation of the device in this situation. In this case, both RS flip-flops are brought into a single state. At the outputs of elements And 8.9, single signals are generated that arrive at the J-inputs of JK triggers 3 and 4, respectively. At the trailing edge of the next pulse from input 13 of the device, the T-trigger 5 changes its state and the front one appears at its output or the back Front of a single clock signal. If this is a rising edge, then the first of the received requests will execute a read request. On the leading edge of the clock signal from the output of the T-flip-flop 5, the JK-flip-3 goes into a single state. Accordingly, a signal is generated at the output of the device 14, which controls the reading from the buffer memory. The translation of the JK trigger 4 into a single state is blocked, because the zero signal from the inverse output of the JK trigger 3 closes the And 9 element and the single write request signal at the J-output of the JK trigger 4 disappears. A request from a write is awaiting execution in flip-flop 2 until reading from the buffer memory has finished. In the event that, after receipt of triggers 5 and 4 at the J-inputs, the leading edge of the signal from the output of the T-trigger 5 is the first, then, similarly to the described, the first device generates a write control signal to the buffer memory, and the read request awaits completion

0 entries in RS trigger 1.

Thus, when expressions (5) and (6) are satisfied, the device separates in hardware at runtime, without failures, all requests received for it

5 writing and reading data from the buffer memory from the source and receiver of information operating asynchronously and independently of each other.

Claims (1)

0 Claims A device for dividing in time write and read requests containing RS read and write triggers. JK - read and write triggers, T-trigger. moreover 5, the dividing frequency input of the device is connected to the T-input of the T-flip-flop, the output of which is connected to the clock inputs of the JK-write and read triggers, the read and write request inputs are connected to the S-inputs of the RS-read and write triggers, direct outputs JK read and write triggers are connected to the R-inputs of the corresponding RS-read and write triggers, as well as outputs respectively 5, for controlling the reading and writing of the device, the K-inputs of the JK read and write triggers are connected to the zero potential bus of the device, characterized in that it contains a counter, an OR element, first 0 third AND elements, and the direct outputs of the J K-read and write triggers connected cf- responsibly with the first and second inputs of the OR element, the output of which and the input of the dividing frequency of the device are connected 5, respectively, with the first and second inputs of the third AND element, the output of which is connected to the counter input of the counter, the output of the counter is connected to the asynchronous R inputs of the JK read and write triggers, outputs 0 J K-read and write triggers are connected respectively to the first inputs of the first and second AND elements, the outputs of which are connected respectively to J-exoflSMH, JK read and write triggers, inverse The 5 outputs of the JK triggers for writing and reading are connected respectively to the second inputs of the first and second elements I. Sv1. .3 -fV . : .sh.  i “h; -. "