RU1833878C - Device for numerical circuits control - Google Patents

Abstract

The invention relates to automation and computer engineering. To the serial circuit, a long trigger, tools have been added that provide the possibility of self-testing. 5 ill.

Description

The invention relates to computer technology and can be used to build testable logic devices.

The purpose of the invention is to increase testability.

Figure 1 shows a functional diagram of a device; figure 2 is a functional diagram of a long trigger; in Fig. 3 is a functional diagram of a discriminator; FIG. 4 is a timing diagram of a device check; figure 5 is a timing diagram of the operation of the discriminator,

The device contains (Fig. 1) a controlled circuit (long trigger) 1, delay line 2, pulse shapers 3, 4 and 5, discriminators 6 and 7, adder 8 modulo two, source 9 of the reset pulse, has information inputs 10 and outputs 11 diagnostic input 12, diagnostic output 13.

Line 2 has a delay T.

Each of discriminators 6 and 7 has sync inputs 18. 19, reset input 20, output 21.

Shapers 3 and 4 can be made in the form of differentiating chains or in the form of differentiating transformers. The purpose of each of these shapers is to transmit (in the form of a short-term (in duration much shorter than T) logical O) a slice of the output pulse to the output.

Shaper 5 can be made in the form of an integrating chain. Its purpose is to transmit from output 24 to output 13 only pulses of duration no less than T.

Each of discriminators 6 and 7 contains (FIG. 3) triggers 27 and 28, delay element 29.

The source 9 is designed to generate a reset pulse at the moment of power-up of the device.

. Element 29 may be made in the form of an integrating chain.

In operation, the device is used for its intended purpose (as a prototype). At the same time, O is held at input 12.

The device is checked against multiple constant failures of the logic elements according to Fig. 4.

We denote by t the delay of the logical signal on the path 14-16 and on the path 15-17. The delay element 29 of each of the discriminators 6 and 7 should be equal to 3/2 g The relationship between T and g should correspond to Fig. 4. We assume that N (figure 2)

to

00

with

(AND)

so large that propagation delays along path 18-21 can be neglected.

Before the start of the test interval, O is detected on the odd inputs 10 (indicated in FIG. 4 through 10), and 1 is fixed on the even inputs 10 (indicated in FIG. 4 through 10). In the interval t, the inputs 10 are in the opposite state, which stored until the end of the check interval.

The test interval begins with the input to the input 12 of the pulse I1 of duration r, where r T.

If the device is operational, then further occurs in accordance with figure 4, namely: the pulse I1 passes to the input 18 of the discriminator 6 And, passing along the path 14-1.6, goes to the input of the driver 3 in the form of a pulse I2. The slice of the pulse I2 through the shaper 3 acts on the input 19 of the discriminator 6, causing the discriminator 6 to switch to the opposite state. This causes a switch to the opposite state of the adder 8.

In addition, pulse I1 passes through line 2 in the form of a pulse of IZ, which enters the input 18 of discriminator 7 and, passing along path 15-17, enters the input of former 4 acts on input 19 of discriminator 7, causing the discriminator 7 to switch to the opposite state . This causes a switch to the opposite state of the adder 8.

As a result, the adder 8 generates a pulse of duration T, which passes through the former 5 to the output 13.

In this case, each of the discriminators 6 and 7 operates in accordance with Fig. 5, where tc27 and tc28 are the operation delays of the triggers 27 and 28 (for the correct operation of the device, it is necessary that the response, preset and hold times of the triggers 27 and 28 be much less than 1/2 t).

In relation to discriminator 6, pulse I1 is designated through I18, and pulse I of short-term logical O selected by driver 3 under the influence of pulse strobe I2 through I19.

In relation to the discriminator 7, the IZ pulse is indicated through I18, and the short-term logical O pulse generated by the driver 4 under the influence of the I4 pulse gate is indicated by I19,

The end of pulse J18 causes the state of trigger 28 to be received in trigger 27. While the change in state of trigger 27 passes through element 29, the beginning of the pulse

I19 causes entry into trigger 28 of the old state of trigger 27, i.e., after passing through a pair of pulses I18 and I19, the output 21 of the discriminator switches to the opposite state.

The following discriminator properties are important:

if the discriminator is in good condition, failure to receive a cut-off of the pulse at the input 19 for approximately the time after the cut-off of the pulse is received at the input 18 causes the discriminator to become a generator of a logical constant;

with constant failures of its logical elements, the discriminator loses its ability to form pulses, at least pulses of a longer duration than pulses I18 and I19.

Let output 13 observe a pulse of duration T.

This indicates the serviceability of the driver 5, the adder 8, discriminators 6 and 7 and the drivers 3 and 4, and also that the signals at points 14-17 correspond to FIG.

Since it turns out that a complete test is being performed for controlled circuit 1, it has been fixed. In addition, a good line 2.

And the appearance at the output 13 of a pulse with a duration of T, following the supply of an I1 pulse to input 12, clearly indicates the serviceability of the device.

Claims (1)

Claims A device for monitoring digital circuits, comprising an adder modulo two, characterized in that, in order to increase the depth of control, the device contains a delay line, three pulse shapers, two discriminators, and the diagnostic input of the device is connected to the first resolution input of the controlled digital circuit, with the first through the inlet of the first discriminator, and through the delay line with the second enable input of the controlled digital circuit and with the first inlet of the second discriminator, the first control point controlled digital circuit connected to the input of the first pulse shaper, the output of which is connected to the second input of the first discriminator, the output of which is connected to the first input modulo two adders, the second input of which is connected to the output of the second discriminator, the second clock input of which is connected to the output of the second pulse former, the input of which is connected to the second control point digital circuit, the output of the adder modulo two is connected to the input of the third pulse former, the output of which is the error output of the device, the reset input of the device is connected to the reset inputs of both discriminators. FIG. 2 ftsg. 3 Interval check FIG. 5