RU1800643C - Device for stimulating frequency-modulated signals - Google Patents

Abstract

Usage: in the technique of data transfer. SUMMARY OF THE INVENTION: the device comprises a band-pass filter, a pulse shaper, a frontal separation unit, a counter, a first arithmetic unit, a second counter, a clock, a coefficient calculation unit, four comparators, an analysis unit. The device provides the ability to decide on the significance of each received information packet in the demodulation process. 9 ill.

Description

Joint venture

with

The invention relates to data transmission techniques and can be used in frequency-modulated signal converters.

The purpose of the invention is to make it possible to decide on the significance of each received information packet in the process of demodulating frequency-manipulated signals.

In FIG. 1 is a functional diagram of a device for demodulating frequency-manipulated signals; in FIG. 2 is an embodiment of a particular embodiment of the edge allocation unit; in FIG. 3 - coefficient calculation unit; in FIG. 4 - signal analyzer; in FIG. 5 - arithmetic unit; in Fig.6 - recording unit; in FIG. 7 - clock generator; in FIG. 8 and 9 are time diagrams explaining the operation of the device.

A device for demodulating frequency-manipulated signals comprises a band-pass filter 1, a pulse shaper 2, a front allocation unit 3, a counter 4, a coefficient calculation unit 5, the first and second arithmetic units 6 and 7, the first, second, third and fourth comparators 8-11 , signal analyzer 12, counter 13, clock 14.

The edge selection unit 3 may be implemented, for example, as shown in FIG. 2, and contains sequentially connected triggers 15.1 ..... 15.4, forming a shift register, elements I16, I17, I18, I19.

The coefficient calculation unit 5 (see, Fig. 3) contains two read-only memory blocks ROM 20 and ROM 21, as well as a delay element 22.

The signal analyzer 12 (see Fig. 4) contains two elements 2I-IL AND 23 and 33, six elements 26, 29, 31, 35, 36 and 39 and nine elements OR 24, 25, 26, 28. 30, 32, 34, 37 and 38.

00

Ltd

N WITH

Each arithmetic block b (7) (see Fig. 5) contains a multiplexer 40, an adder 41, a register 42, and an OR element 43.

The recording unit 13 (see FIG. 6) is a shift register 44,

The clock generator 14 (see FIG. 7) comprises a reference oscillator 45 and a divider 46 connected in series.

The proposed device operates as follows.

The frequency-manipulated signal coming from the communication channel (Fig. 8b) passes through a bandpass filter 1, is converted by a pulse shaper 2 into rectangular pulses, which are fed to the input of the edge selection unit 3.

At the moment the frequency-manipulated signal passes through the zero level, the edge selection unit 3 generates at its outputs from the pulses of the reference frequency fon coming from the second output of the clock generator 14, the series of pulses shown in FIG. 8, c, d, e, e. According to the pulses generated at the second output of block 3 (Fig. 8, c), the contents of the counter 4 go to the coefficient calculation unit 5, and according to the pulses generated at the first output of block 3 (FIG. 8f), the counter 4 is reset and starts counting the clock pulses fT coming from the first output of the clock generator 14. Thus, the periods of the frequency-manipulated signal are converted into the number of clock pulses fr.

For normal operation of the device, it is necessary to fulfill the ratio fon 5: fT, which allows the generation of pulses (Fig. 8, c, d, e, f) in the block 3 of the selection of fronts for one period of the frequency fT.

In the general case, each period of the received frequency-manipulated TPR signal (see Fig. 9) is identified with the period in which the characteristic frequencies fi and fa change. Then, assuming that at the time ti of the characteristic frequency change, there is no phase discontinuity (this condition is usually fulfilled), the length of the received signal period is determined by the following relation:

TPr Kg Ti + K2 T2, (1) where Ki, K2 are coefficients that take into account which part of the periods Ti and Ta of the characteristic frequencies fi and fa respectively correspond to the received period. In this case, for the coefficients Ki and K2, the following relation is satisfied:

Ki + Ka 1

5

10

fifteen

20 25 30

35

40 45 50

55 Similar relations (1) and (2) are valid for half-periods of a frequency-manipulated signal.

Having preliminarily solved equations (1) and (2) together, for each value of the adopted period TPr, the values of the coefficients Kch and Ka by formulas (3) and (4) are found: TPr - Ta

Ki

(3)

3)

4)

Ti - Ta.

Provided that TI Ta, the coefficients Ki and Ka take the following values:

1) Ki 1, Ka 0 at TPR Ti;

2) Ki 0, Ka 1 with Tpr Ta; 0 Ki 1 npnTa Tnp Ti; 0 Ka 1 at Ta TPr TC

5) Ki Ka 0 when TPR Ti or TPR Ta.

Expressing the values of the periods Ti, Ta, Tpr through the number of pulses N of the clock frequency fT, arriving at counter 4, and substituting them into formula (3), we obtain the final expression for finding the coefficients Ki and Ka:

 (5)

fr iDJ

Na fT; Nnp. ()

Ta

(6)

Tp Ki

K2

fT Nnp - N2 N1 -Na N1 -Nnp

(8)

(9)

N1-N2

where Ni, Na, Nnp is the number of pulses of the frequency fr of the clock generator, respectively, corresponding to the period Ti, Ta, TPr.

The values of the coefficients Ki and Ka calculated by formulas (8) and (9) are written respectively in the first and second ROM 20, 21 of the coefficient calculation unit 5 (Fig. 3).

Upon receipt of an impulse from the second output of the edge selection unit 3 (Fig. 8, c) to the coefficient calculation unit 5, the coefficient values Кч and Ка recorded at the address Nnp corresponding to the duration of the received period Тпр are read out in the first and second ROMs 20, 21 (FIG. . 8, g, 8, and) and respectively arrive at the first and second arithmetic units 6 and 7, where the pulse also arrives (Fig. 8 „c), delayed by the delay element 2. In FIG. 8, this delay is not reflected due to its small size.

In the first and second arithmetic blocks 6 and 7, the values of the coefficients Ki and Ka through the multiplexer 40 are fed to the input of the accumulating adder formed by the adder 41 and the register 42. At the same time, by the delayed pulse (Fig. 8, c),

received through the OR element 43 to the clock input of the register 42, the current values of the coefficients Ki and K2 are summed up with the previous values of the coefficients Ki and K2. In FIG. 8c shows how a change in the sum of the coefficients KI and 2 2, respectively, occurs.

After summing, the resulting sums of the coefficients Ki and K2 are compared with threshold values of the coefficients by comparators 8-11. In this case, the comparators 8 and 9 compare the sum of the coefficients Ki, respectively, with the value of the lower threshold KiH and the value of the upper threshold Ku, and the comparators 10 and 11 compare the sum of the coefficients K2, respectively, with the values of the lower threshold K2n and the values of the upper threshold K2b.

The values of the upper thresholds K- | B and K2b are determined by the relations (10) and (11):

(YU)

.-§:

,

where B is the manipulation rate, bit / s.

The values of the lower thresholds of Kn are established empirically depending on the expected state of the communication channel and are (0.9-0.95) the values of the upper thresholds of Qu.

The output signals of the comparators 8-11 are supplied to the corresponding inputs of the signal analyzer 12, which at the moment of arrival of the strobe pulses (Fig. 8, e, d), respectively, from the third and fourth outputs of the edge selection unit 3, checks the comparison conditions by comparators 8-11 and provides the corresponding signals to information and clock outputs and to outputs one through six.

If, after the next summation, the sum of the Ki coefficients satisfies condition 2 Ki K-IB, then the KiB values are subtracted from the sum of the Ki coefficients, and the sum of the K2 coefficients is corrected to the current K2 value. At the same time, a high level signal appears at the third or fourth input of the signal analyzer 12, which, through the second OR element 25, enters the third output of the analyzer 12, the first input of the first And 26 element, and through the first OR element 24, to the information output of the analyzer 12 signals (Fig. 8, n) and the first input of the third element And 31.

The pulse (Fig. 8, d) entering the second gate input of the signal analyzer 12 passes through the third element AND 31, the sixth element OR 32 per clock

the output of the analyzer 12 (Fig. 8, m) and writes logical 1 to the first stage of the shift register 44 (Fig. 8, p). At the same time, the pulse (Fig. 8, g) enters through the eighth

. 5, an OR element 37 to the sixth output of the analyzer 12 and sets the register 42 of the second arithmetic unit 7 to the zero state.

The pulse (Fig. 8, e), arriving at

10, the first gate input of the signal analyzer 12 passes through the first element AND 26, the third and fourth elements OR 27, 28 and enters the second and fifth outputs of the analyzer 12. This leads to

15 of the first arithmetic unit 6, the KiB value is subtracted from the accumulated sum of the Ki coefficients, since the high-level signal supplied to the fifth input of the first arithmetic unit 6 switches

20, the multiplexer 40 and the number (-Ktv) is supplied to its output, and the value K- | B is subtracted from the sum of the coefficients Ki by the pulse (Fig. 8e).

Simultaneously by impulse (Fig. 8, d)

25, the second arithmetic unit 7 of the current value K2 is recorded in register 42. In FIG. 8c, l show changes in the sum of the coefficients Ki and K2, respectively.

30 If, after the next summation, the sum of the coefficients Ki satisfies the condition KIH S 2 Ki KiB, then the sum of the coefficients Ki is reduced to zero, and the sum of the coefficients "2" is adjusted to the current value of K2. At the same time, a high-level signal appears at the first or second input of the signal analyzer 12, the passage of which to the output of the first 2-OR-23 element permits a high-level signal

40 level, coming from the fifth input of the signal analyzer 12. The high-level signal from the output of the first element 2 AND-OR 23 goes to the first input of the second element And 29 and through the first element OR 24 to

45, the first input of the third element And 31 and the information output of the analysis unit 12 (Fig. 8, n).

The pulse (Fig. 8, g), arriving at the second gate input of the analysis unit 12,

50 passes through the third element And 31, the sixth element OR 32, to the clock output of the analyzer 12 (Fig. 8, m) and writes logical 1 to the cascade of the shift register 44 (Fig. 8, p). Simultaneously, the pulse (Fig. 8, g)

55 enters through the eighth OR element 37 to the sixth output of the analyzer 12 and sets the register 42 of the second arithmetic unit 7 to the zero state.

The pulse (Fig. 8, e), arriving at the first gate input of the analyzer

12 passes through the second AND element 29, the fifth OR element 30 to the first output of the analysis unit 12, and from the output of the second AND 29 element through the fourth OR element 28, to the fifth output of the analyzer 12. This leads to the first arithmetic unit 6, the register 42 is set to the zero state (the sum of the coefficients Ki is reduced to zero), and in the second arithmetic unit 7, the current value K2 is written to the register 42.

If, after the next summation, the sum of the coefficients Kt satisfies the condition SKi KiH, then the sums of the coefficients Ki and "2 do not change, since low-level signals are present at all inputs of the signal analyzer 12. Therefore, the pulse (Fig. 8, d) does not pass to the clock output of the signal analyzer 12, i.e., there is no pulse (Fig. 8, m).

If, after the next summation, the sum of the coefficients K.2 satisfies the condition Z К2в, then the value “2в is subtracted from the sum of the coefficients“ 2, and the sum of the coefficients Ki is corrected to the current value KL. A signal appears at the sixth or seventh input of the analyzer 12 high level, which through the ninth element OR 38 enters the fourth output of the analyzer 12, at the first input of the sixth element And 39 and through the seventh element OR 34 to the first input of the fourth element And 35.

The pulse (Fig. 8, d) arriving at the second gate input of the analyzer 12 signals passes through the fourth element AND 35, the sixth element OR 32 and arrives at the clock output of the analyzer 12 (Fig. 8, m) and writes it to the shift register 44 logical O. At the same time, a pulse (Fig. 8d) is transmitted through the fifth element OR 30 to the first output of the signal analyzer 12 and sets the register 42 of the first arithmetic block b to the zero state.

The pulse (Fig. 8, e) arriving at the first gate input of the analyzer 12 passes through the sixth element AND 39, the third and fourth elements OR 27, 28 to the second and fifth outputs of the analyzer 12. Moreover, in the second arithmetic unit 7 from the accumulated the sum of the coefficients K2 subtracts the value of K28, because a high-level signal supplied to the fifth input of the second arithmetic unit 7 switches the multiplexer 40 and the number (-K2v) is output, and the pulse (Fig. 8, e) subtracting from the sum of the coefficients "2 the value of K2b. At the same time, the pulse (Fig. 8e) is recorded in

register 42 of the first arithmetic block b of the current value KL

If, after the next summation, the sum of the coefficients K2 satisfies the condition K2n 2 K2 K2v, then the sum of the coefficients K2 is reduced to zero, and the sum of the coefficients KI is adjusted to the current value KL

At the same time, at the ninth or tenth input of the analyzer 12, a high-level signal appears, the passage of which to the output of the second 2-OR-33 element allows a high-level signal coming from the eighth input of the analyzer 12. A high-level signal from the output of the second 2-OR 33 enters the first input of the fifth element And 36 and through the seventh element OR 34 - to the first input of the fourth element And 35.

The pulse (Fig. 8, d), arriving at the second gate input of the signal analyzer 12, passes through the fourth element AND 35, the sixth element OR 32 to the clock output of the analyzer 12 (Fig. 8, m) and writes logical 0 to the cascade of the shift register 44 (Fig. 8, p). At the same time, a pulse (Fig. 8d) enters through the fifth OR element 30 to the first output of the analyzer 12 and sets the register 42 of the first arithmetic unit 6 to the zero state,

The pulse (Fig. 8, e), arriving at the first gate input of the signal analyzer 12, passes through the fifth element AND 36, the eighth element OR 37, and enters the sixth output of the analyzer, and from the output of the fifth element AND 36 through the third element OR 27 - to the second output of the analyzer 12. In this case, in the second arithmetic unit 7 of the register 42 it is set to the zero state (the sum of the coefficients K2 decreases to zero), and in the first arithmetic unit 6 the current value KL is written to the register 42

If, after the next summation, the sum of the coefficients K2 satisfies condition 2 K2 K2H, then the sums of the coefficients KI and K2 do not change.

After checking the conditions, the first input of the counter 4 receives a pulse (Fig. 8, e), which sets it to the zero state, after which the counter 4 again counts the pulses of the clock generator 14, measuring the duration of the next period of the frequency-manipulated signal and described above the process is repeated.

Thus, the proposed technical solution allows the device for demodulating frequency-manipulated signals to make a decision on the value

each received information package during the demodulation of the frequency-manipulated signals, and the receipt of pulses at the time of making a decision on each received package allows you to exclude synchronization devices in the communication system in which the proposed device is used, which simplifies the system as a whole.

In addition, unlike the prototype device, the proposed device eliminates the possibility of reducing the actual data transfer rate, since there is no need to enter synchronism of synchronization devices upon entering into communication.

Claims (2)

The claims 1. A device for demodulating frequency-manipulated signals, containing a series-connected bandpass filter, the input of which is the input of the device, a pulse shaper, a fronting unit, to the clock input of which one output of the clock generator is connected, and a counter, to the clock input of which another output of the clock generator is connected, as well as a first arithmetic unit and a recording unit, the outputs of which are the outputs of the device, characterized in that, in order to enable decisions on the value of each information package, a signal analyzer, a second arithmetic unit, four comparators and a coefficient calculation unit are introduced, the inputs and outputs of which are connected respectively to the second output of the edge selection unit and the counter outputs and to the information inputs of the first and second arithmetic units, to control the inputs of which are connected one of the outputs of the signal analyzer, information and control inputs and other outputs of which are connected respectively with the outputs of the comparators, with the third and the fourth outputs of the edge selection unit and with the inputs of the recording unit, while the outputs of the first and second arithmetic units are connected respectively to the information inputs of the first and second and third and fourth comparators, the threshold inputs of which and the threshold inputs of arithmetic units are the threshold inputs of the device. 2. The device pop. 1, characterized in that the coefficient calculation unit comprises two constant memory blocks and a delay element, the input of which and one of the inputs of the constant memory blocks are inputs of the coefficient calculation block, the outputs of which are the outputs of the constant memory blocks and the output of the delay element whose input is combined with other inputs of read-only memory blocks. 53. The device according to claim 1, with the proviso that each arithmetic unit contains an OR element and series-connected multiplexer, adder and register, the second input and outputs of which are connected respectively with the output of the OR element and with the second inputs of the adder, which are the outputs of the arithmetic unit, the information and control inputs of which are 5, respectively, one input of the multiplexer and the first input of the OR element and the third input of the register, the second input of the OR element and the other input of the multiplexer, the threshold input of which is the threshold input of the arithmetic block. 4. The device according to p. 1, characterized in that the signal analyzer contains two elements 2 AND-OR, six elements AND and nine elements OR, while the output 5 of the first AND-OR element 2 is connected to the first input of the first OR element, the second input of which is connected to the output of the second OR element and to the first input of the second AND element, and to the first input of the second AND element, the second input and output of which are connected respectively to the second input the first AND element, the output of which is connected to the first input of the third OR element, and the first input of the fifth OR element, the second input of which is connected to the output of the fourth AND element, which is connected to the second input of the sixth OR element, the first input of which connected to the output of the third AND gate, to the first 0 the input of which the output of the first OR element is connected, and with the first input of the eighth OR element, the second input of which is connected to the third input of the third OR element, the second input of which is connected to 5 to the third input of the fourth OR element, and with the output of the fifth AND element, the first input of which is connected to the second input of the second AND element and with the second input of the sixth AND element, the first input and output of which are connected respectively with the output of the ninth OR element, which is connected to the first input of the seventh OR element, and with the third input of the fourth OR element, the second and first inputs of which 5 are connected respectively to the outputs of the second and first AND elements, and the output of the second AND-OR element 2 is connected to the second input of the fifth AND element and to the second input of the seventh OR element, the output of which is connected to the second input of the fourth element And, the first input of which is connected to the second input of the third element And, the outputs of the second, third, fourth, n, whose equal inputs are respectively the outputs of the first and sixth elements OR, the inputs of the first and second the eighth and ninth OR elements are 2AND-OR elements and the inputs of the second and virgins with one outputs of the signal analyzer, the 5th OR elements and the second and first inputs are the other outputs and the information and outputs of the sixth and fourth elements I. from 2 ---- 7 FIG. 2 whose equal inputs are respectively the outputs of the first and sixth elements OR, the inputs of the first and second 2 AND-OR elements and inputs of the second and maids FIG. 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