SU1288926A1 - Synchronizing device - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to improve noise immunity. The device contains a reference r-1, a divider 2 frequencies, a driver (F) 3 gating pulses, a counter 4, F 5 pulses on the leading edge of the signal, F b pulse on the falling edge of the signal, two elements And 7 and 8 and RS- trigger 9. The protection of a synchronization device against possible impulse noise is achieved by closing element I 7 for the duration of the formation of a "single pulse at the device output. 2 Il. fPu2.1 N3 СХ) 00 g y O5

Description

The invention relates to the field of telecommunications and can be used in data transmission systems for synchronizing clock pulses.

The aim of the invention is to improve the noise immunity.

Figure 1 shows the structural electrical circuit of the synchronization device; in fig. 2 - timing charts of signals, explaining the operation of the synchronization device.

The synchronization device contains a reference generator 1, a frequency divider 2, a gating pulse shaper 3, a counter 4, a shaper shaper 5 on a leading edge of the signal, a shaper 6 pulses on a falling edge of the signal, the first 7 and second 8 elements And, RS flip-flop 9.

The synchronization device operates as follows.

In the initial state, the RS flip-flop 9 (Fig. 1) is in the state "O and the first element AND 7 is open. The pulses from the output of the reference generator 1 are fed to the counting inputs of divider 2 and counter 4. From the first output of divider 2, a pulse sequence is applied to the input of shaper 3 with a frequency twice the follow frequency of the input pulses, resulting in the shaper 3 output Gating pulses corresponding to the middle of the input parcels (Fig. 2h).

When a discrete information signal arrives at the input of the synchronization device (input packages, Fig. 2a), pulses (Fig. 26) appear at the output of shaper 5, which through the open first element And 7 arrive at the installation inputs of divider 2 and count 4 and set them in the initial state. The output of the counter 4, counting up to m pulses, corresponding to the duration of the input parcel TO, is impacted by a pulse (FIG. 2d), which goes to the second input of the second element And 8, simultaneously to the first input of which impulse, formed by shaper 6 ( figb). The impulse of coincidence with the output of the second element And 8 (Fig. 2e) is fed to the S input of the RS flip-flop 9 and translates it into the state "1, resulting in

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At the output of the synchronization device, a “Single impulse (FIG. 2e)” is formed, and the “Zero signal from the inverse output of the RS flip-flop 9 (FIG. 2g) closes the first element And 7 at the formation time, protecting the synchronization device from possible impulse noise. Through n pulses of the reference generator 1, where n "2m 2to, at the second output of the divider 2, a Vits pulse (Fig. 2i), which, arriving at the R input of the RS flip-flop 9, will transfer it to the" O "state The first element And 7 will open and the synchronization device will be ready to receive the next information packet.

If, at the input of the synchronization device, a pulse disturbance appears, the pulse duration of which is Tto or tto, then. as a result, the pulse from the output of the counter 4 and the pulse from the output of the imaging unit 6 will not coincide, and the RS-flip-flop 9 will remain in the initial state, i.e., no changes will occur at the output of the synchronization device.

Claims (1)

Invention Formula A synchronization device containing its serially connected reference oscillator and a frequency divider connected in series to a pulse shaper on the leading edge of the signal and the first And element, sequentially connected to a pulse shaper on the falling edge of the signal, the second And element and the RS flip-flop, as well as a counter, counting and The installation inputs of which are connected respectively to the output of the reference generator and the installation input of the frequency divider, and the combined inputs of the pulse shaper on the leading edge of the signal The ala and impulse generator on the falling edge of the signal is the device input, the output of the frequency divider is the output of the device, differing in bodies; to increase noise immunity, the additional output of the frequency divider is connected to the R input of the RS flip-flop, the inverse output of which is connected the second input of the first element is And, the output of which is connected ;; sn to the combined setup inputs of the frequency divider and the counter, and the output of the counter is connected to the second input of the second eleme.meit I. a 5 g g d e Well 3 and with 111 .1 FIG. 2