RU1780158C - Pulse synchronizer - Google Patents

Abstract

The invention relates to a pulsed technique and can be used in pulsed information processing devices. The device comprises a pulse generator 1, a group of 2 AND elements, a synchronizer 3, registers 4, 5. 6, an OR element 7. a group of 8 comparison elements, comparison elements 9, 10, counters 11, 12 pulses, an And 13 element, trigger 14. decoder 14. 15. a group of 16 counters, an input bus 17, coding buses 18, 19. installed installation buses 20. output buses 21. 22 about corresponding communications. 1 ill.

Description

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The invention relates to a pulsed technique and can be used in pulsed information processing devices.

A device for synchronizing a pulse-EZ is known, comprising a multiphase pulse generator, a group of AND elements, a storage register, and an OR element 1.

The disadvantages of the known device are low accuracy of synchronization and noise immunity and narrow functionality.

The closest in technical essence to the claimed is a device for synchronizing pulses containing a pulse generator, a short pulse generating unit, two OR elements, a storage register and a group of AND elements, as well as a synchronizer 2.

The disadvantages of the known device are low noise immunity, as well as narrow functionality, since the known device does not allow the formation of pulses of a given duration and duty cycle.

The purpose of the invention is to increase noise immunity and expand functionality by additionally generating synchronized pulses of a given duration and duty cycle;

The goal is achieved in that a pulse synchronization device comprising a pulse generator, a first register, an OR element, a group of AND elements, a synchronizer, the control input of which is connected to the input bus, the first output bus, the first and second pulse counters, the first and second elements sapeni, trigger, decoder, second and third registers, element And, a group of N pulse counters and a group of N comparison elements, and the output of the pulse generator is connected to the counting input of the first pulse counter, with the synchronizer and with the first input, the element And, the output of which is connected to the counting input of the second pulse counter, the outputs of which are connected to the first group of inputs of the first bias element, the second group of inputs of which are connected to the output, the first register, the information inputs of which are connected to the first the code bus, the sync input is with the first installation bus, the output of the first comparison element is connected to the installation input of the second pulse counter vt with the R-input of the trigger, the direct output of which:: oe / | n iOH with the second input nta And with the first output and; another, S-input - with the second output (; th AND WITH THE OUTPUT of the second comparison element, the first group of inputs of which is connected to the outputs of the second register, the information inputs of which are connected to the second group of inputs of the second

a comparison element, with the outputs of the first pulse counter and with the inputs of the decoder, the outputs of which are connected to the first inputs of the corresponding elements AND groups of N elements AND, the second inputs

0 of which are connected to the output of the synchronizer, outputs are connected to the counting inputs of the respective pulse counters, groups of N pulse counters, the outputs of which are connected to the first groups of inputs of the corresponding comparison elements, a group of N comparison elements, the second groups of inputs of which are connected to the outputs of the third register, information inputs which are connected to the second code

0 bus, the sync input is with the second installation bus, the outputs of the comparison elements of a group of N comparison elements are connected to the inputs of the OR element, the output of which is connected to the sync input of the second register and

5 with an R input of pulse counters of a group of N pulse counters.

The drawing shows a structural diagram of a device for synchronizing pulses,

0 The device for synchronizing pulses contains a pulse generator 1, a group of 2 AND elements, a synchronizer 3, a second register 4, a third and a first register 5 and b, an OR element 7, a group of 8 elements equal to 5 nm, the second and first comparison elements 9 and 10, the first and the second counters 11 and 12 pulses, the element And 13, the trigger 14, the decoder 15, a group of 16 counters, the input bus 17, the second and first code buses 18

0 and 19, the first and second installation bus

20, first and second output buses 22 and

21. Synchronizer 3 contains a trigger and an element I.

The device operates as follows.

By pulses from the generator 1, the counter 11 organizes cyclically from O to N-1, for each of the N states of the counter 11 at the corresponding output of the decoder 15

0, a positive signal is generated, opening the corresponding AND element of group 2.

RHODNSY synchronized impulse pos. - iBT on device bus 17 and setting 5 ... trigger of synchronizer 3 in a single state. The next subsequent pulse from the output of the generator 1 comes through the element A synchronized, opened by the trigger of the synchronizer; the corresponding output of the decoder 15, The signal from the output of the element AND of group 2, the corresponding counter of group 16 increments its contents. In the initial state, the triggers, counters and register 4 are reset / the corresponding initial setting circuits are not shown in the drawing. Before the device starts to work, a binary code of the number / which determines the necessary number of pulse repetitions at a certain position is entered into register 5, so that the device decides on the reliability of the location of the input pulse at this particular time position. Similarly, a binary code of the number corresponding to the duration of the output pulse of the device, expressed as the number of clock pulses from the generator i, is entered into register 6.

As described above, the pulses at the input 17 of the device are distributed among the AND elements of group 2 and are counted separately for all time positions by the counters of group 16. The numbers contained in the counters of group 16 are compared on the comparison elements of group 8 with the criterion value from register 5. 3 moment the time when the contents of one of the counters of group 16 becomes equal to the contents of register 5, the corresponding element of comparison of group 8 is triggered and, through the element OR, 7, the position number in which, according to the criterion, it is detected with the required degree of reliability VILS synchronized pulse sequence signal from the AND recorded with the counter 11 outputs to the register 4; in this case, since the co-obsession of the counter 11 and register 4 becomes equal, a signal appears at the output of the Comparison element and the output 21 of the device arrives, linking the input pulse to the clock sequence of the generator 1.

In the event that before the appearance of a reliable pulse at the input of the device at the output of the device no initial pulses should be formed, before starting the operation of the device, enter a number in register 4 that is different from any code in counter 11, for example, a binary code of the number N + 1.

By the signal from the OR element 7, the counters of group 16 are reset to the initial (zero) state, the analysis of the new reliable position of the pulse begins first, in the future, if there are no input pulses at the input 17 of the device, the output 21 of the device generates pulses with

period N That, where N is the capacity of the counter 11, and That is the pulse repetition period from the generator 1, The duration of the output pulses at the output of the comparison element 9 pa8; -; s the period of the signals from the output of the generator 1.

At any moment in time, subsequently, the triggering element of the comparison element (of any) of group 8 causes a change in the number of the position at which the device generates a pulse from output 21 in the same way.

Blocks 6, 10,12 14 realize the formation of an impulse of the required duration. The signal from the output 21 sets the trigger 14 to a single state, opening the And 13 element through which pulses from the generator 1 begin to arrive at the counter 12. At the moment of the contents of the counter 12 and the register 6 coinciding, the comparing element 10 is activated and resets the trigger 14 to the zero state nie. Thus, the pulse duration at the output 22 is equal to K That, where K is the contents of the register 6. In particular. when the output pulses at the output 22 have the shape of a meander.

Thus, the inventive device makes it possible to exclude the probability of generated synchronized pulses at the output from random interfering input pulses, moreover, 4 the degree of reliability is selected by the user, which increases the noise immunity of synchronization and the stability of the output pulses. In addition, the device allows the generation of pulses of a given duration to duty cycle.

Claims (1)

The claims Device dg. synchronization of pulses, containing a pulse generator, the first register, the OR element, the group of AND elements, the synchronizer whose control input is ss-one with the input bus, the first output 1Iin, characterized in that, with the aim of increasing noise immunity and expanding functionality by additional formation synchronized pulses of a given duration and duty cycle, it contains the first and second pulse counters, the first and second elements of the comparison, trigger, decoder. the second and third registers, element And, a group of N pulse counters and a group of N comparison elements, and the output of the pulse generator is connected to the counting input of the first pulse counter, to the clock input of the synchronizer and to the first input of the element And, the output of which is connected to the counting the input of the second counter pulses, the outputs of which are connected to the first group of inputs of the first comparison element, the second group of inputs of which is connected to the outputs of the first register, the information inputs of which are connected to the first code bus, the sync input is to the first installed bus, and the output of the first comparison element is connected to the installation input of the second counter pulses with the R-input of the trigger, the direct output of which is connected to the second input of the And element and to the first output bus, the S-input - to the second output bus, with the output of the second comparison element, p first, the group of inputs of which is connected to the outputs of the second register, the information inputs of which are connected to the second group of inputs of the second element of comparison, with the outputs of the first pulse counter and with the inputs of the Decoder, the outputs of which connected to the first inputs of the corresponding AND elements of a group of N elements AND, the second inputs of which are connected to the output of the synchronizer, the outputs are connected to the counting inputs of the respective pulse counters of the group of pulse counters, the outputs of which are connected to the first input groups of the corresponding comparison elements of a group of N comparison elements, the second groups of inputs are connected to the outputs of the third register, the information inputs of which are connected to the second CODE bus, the sync input is connected to the bus installed, the outputs lementov comparing groups of N elements the comparison are connected to inputs of the OR gate, the output of which is connected to the clock terminal of the second register and with the R-inputs of the group of N pulses the counters pulse counters.