RU2010423C1 - Pulse selector - Google Patents

Abstract

FIELD: pulse equipment. SUBSTANCE: pulse selector includes analog-to-digital converter 1, unit 2 of selection of minimum value, key 3, delay unit 4, timer 5, input signal wire 6, synchronization wire 7, wire 8 of setting of time delay, clock pulse wire 9, triggering wire 10 and output wire 11. Output of analog-to-digital converter 1 is simultaneously connected to unit of selection of minimum value and to delay unit. Each sequence is memorized and formation of result of selection uses data of preceding (memorized) and current sequences data which are entered into delay unit as soon as it is released from data of preceding sequence. EFFECT: reduced selection time. 4 dwg

Description

 The invention relates to a pulsed technique and can be used to isolate pulsed periodic signals from interference.

 A pulse selection device is known, consisting of n parallel-connected delay lines and a coincidence circuit of n pulses. The disadvantage of this device is the restriction imposed on the shape of the input signals matching circuit.

 Another signal accumulation device (recirculator) is known, comprising an adder, a gear coefficient matching device and a delay device.

 The disadvantages of this device are the length of the process of eliminating interference due to the need for many cycles of summing the signals to achieve an acceptable ratio between the levels of useful signals and interference, as well as the inability of the device to change the repetition period of the signal.

 Closest to the proposed technical essence is a pulse selector containing an analog-to-digital converter (ADC), two switches, a device for selecting the lowest signal value, a key device, a delay device, a timer.

 The disadvantage of this device is the delay in detecting the moment of change in the temporary position of the pulses in the selectable pulse sequence.

 A specific feature of this device is the versatility of its operation in various jamming environments, which is achieved by the possibility of varying the number of processed pulse sequences. In a light jamming environment characterized by a small amount of interference, the resulting (selected) signal is formed according to two sequences. Thus, the minimum update period of information at the output of the device is 2T, where T is the period of the pulse sequence. Under conditions of a stable temporal position of signals in sequences, such a delay in updating information at the output of the device is not significant (due to the identity of the obtained waveforms). Under conditions of a sudden change in the temporal position of signals in sequences, a delay in updating the result means a delay (delay) in the detection of the moment of change of the received signal, which is a drawback in cases where it is necessary to quickly identify the moment of change in the signal and obtain information about the new position of the pulses in the sequence .

 Let us consider a special case of solving the problem of selecting periodic pulse sequences from random noise, when the additional conditions are a light noise environment, which allows to obtain satisfactory (good) selection results when processing only two pulse sequences, changing the temporal position of the pulses in the sequences without changing the period of their repetition.

When solving this problem by known means, namely by applying a prototype pulse selector, there is a delay (T _s ) in detecting a signal change due to the fact that the selection result is formed each time according to two sequences (the result is updated at the device output with a period of 2T) .

The delay time (T _s ) depends on the moment the signal position in the sequence changes, as well as the frequency of these changes. Timing diagrams illustrating these relationships in relation to the prototype device are shown in FIG. 1. For simplicity, here, pulse sequences are represented by a single pulse. Therefore, the selection result is formed each time by two sequentially received pulses (in the diagrams, each consecutive pair of pulses is numbered 1 and 2). The first diagram of each option (labeled a, b, c) illustrates the changes in the signals at the input of the device, the second diagram illustrates the processing result recorded at the output of the device during each cycle (equal to the repetition period of signal T) of the device.

 In FIG. 1a shows a change in the position of the signal that occurred during the first period of its processing. The change in the position of the signal is recorded at the output of the device, after one repetition period of the signal T. In the figures, the change in the position of the signal for clarity is shown by an amount exceeding the duration of the signal itself (otherwise, when the offset of the signal does not exceed the duration of the signal, the shape is distorted and reduced signal amplitude, which cannot be reliable and sufficient information about the signal offset).

When the signal changes during the second period (cycle) of the device operation (Fig. 1b), the delay is T _s = 2 T.

 In the first and second variants, the signal position changes with a period greater than or equal to 2T. If the change of signal position occurs more often (<2T), then no useful information is received at the output of the device (Fig. 1c).

From an analysis of the diagrams considered, it can be concluded that, depending on the moment of the signal position change, the delay time T _{s of} detecting this moment is either T, or 2T. In addition, the minimum period of change in the position of signals in sequences, at which the device is guaranteed to perform its functions of selecting signals and providing information about their position, will be 3T (during one selection cycle, equal in duration to 2T, the signal should not change, but taking into account arbitrary character of separation into cycles of the sequence of processed signals receive 3T).

 The technical problem, the solution of which is carried out by the proposed device, is to minimize the time of detection of the moments of change in the temporary positions of the pulses in the pulse sequences and the time to obtain information about their new position, as well as the expansion of the limits of operation by reducing the period of change in the position of the pulses in the sequences.

The proposed pulse selector makes it possible to exclude the dependence of _Tz from the moment the signal position changes (during the first or second period of signal processing), thereby minimizing _Tz to the value of T. At the same time, the device operates while reducing the period of change of position of the pulses in pulse sequences from 3T (in the prototype device) to 2T, i.e., there is an expansion of the limits of functioning.

 The essence of the invention lies in the fact that in the pulse selector containing the ADC, the unit for selecting the lowest signal value and the key, the output of which is connected to the output bus, a delay unit, the first input of which is connected to the ADC start input and the synchronization bus, is connected to the second one the input of the lowest value selection block, a timer whose first input is connected to the start bus, the second input to the clock bus, the third input to the delay time setting bus and the second input of the delay unit, and the output to the input key control, the ADC output is connected with the third input of the delay unit and the input of the lowest value selection unit, i.e., the ADC is simultaneously connected to the lowest value selection unit and to the delay unit. In this case, each sequence is memorized and the selection result is generated according to the data of the previous (stored) and current sequence, the data of which is entered into the delay unit as it is freed from the data of the previous sequence.

 In FIG. 2 shows a block diagram of a pulse selector; FIG. 3 is an embodiment of a timer; in FIG. 4 - waveforms explaining the operation of the pulse selector, where the brackets indicate the waveforms of the signals, according to which the resulting signal is generated (the remaining designations are similar to Fig. 1). The diagram clearly shows a decrease in the response time of the selector (to T to change the position of the signal, as well as the possibility of reducing the period of change of position of the signal (to 2T), at which the selector continues to function (performs selection and provides reliable and timely information about the new position of the signal).

 The pulse selector contains (Fig. 2) sequentially connected ADC1, the lowest value selector 2 and the key 3, the delay unit 4, the output connected to the second input of the unit 2, and the timer 5, the output connected to the control input of the key 3. The ADC input 1 is connected to input bus 6, and the ADC start input 1 is connected to the synchronization bus 7 and to the first input of block 4, the second input of which is connected to the delay time setting bus 8 and the corresponding timer input 5, the third input is with the ADC output 1. There are 9 clock pulses to the bus and start bus 10 are connected respectively inputs of the timer 5. The timer comprises a counter, the digital comparator and the flip-flop. As a comparator can be the use of IC type SP1 (various series) with an inverter for output matching codes.

 The pulse selector operates as follows.

 Before the selector starts, the delay time τ is set (on bus 8), which is equal to the pulse sequence repetition period, which determines the operation parameters of the timer and the delay unit. The operation of the device begins with a start signal (via bus 10), by which the timer generates a control signal for the key device, leading to the opening of its contacts.

 The signal from the input of the selector is converted into an ADC in digital form and fed to the input of the delay unit by τ. The ADC start pulses synchronize the operation of the ADC and the delay unit. After time τ, the timer generates a signal that closes the contacts of the key device, and data on the current (from the ADC) and delayed (from the delay device) signal values reduced by a delay of τ to the same time scale begin to arrive at both inputs of the block for selecting the lowest signal value . The unit for selecting the smallest signal value selects the useful signal components that coincide in time and eliminates random pulse noise that does not coincide in time. The selection result is output 11 of the device. The current signal values simultaneously with the arrival of one of the inputs of the lowest value selection block are entered into the delay block, taking the place of the data released on the previous signal, which are sent to the other input of the lowest value selection block, as two signals are compared.

 Timer 5 operates as follows. At the start signal, the contents of the counter and the trigger are reset. In this case, the trigger output will be a logical "0" (which corresponds to opening the contacts of the key device). When the counter reaches the corresponding value, the comparator generates a code matching signal, which sets the trigger to the logical state “1”. The timer output status remains unchanged until a new device trigger signal.

 Thus, the information at the output of the device changes during each comparison cycle with the period T, which allows you to more quickly receive information about the change in signal position than in the prototype device, where under similar conditions of its operation (similar noise environment) this time can reach 2T . For the same reason, the device can provide information about the change in the position of the signal (while maintaining the selection function) with a shorter period of changes in the positions of the signals in the sequences, namely 2T instead of 3T in the prototype device. (56) Radio interference protection. / Ed. N.V. Maksimova, M.: Sov. radio, 1976, p. 496.

 USSR author's certificate N 1598140, cl. H 03 K 5/26, 1988.

Claims (1)

 PULSE SELECTOR containing an analog-to-digital converter, the input of which is connected to the input bus, the least-value selector and the key, the output of which are connected to the output bus, the delay block, the first input of which is connected to the trigger-input input, are connected in series the output is connected to the first input of the smallest value selection block, a timer, the first input of which is connected to the start bus, the second input to the clock bus, the third input to the bus, setting the delay time and second the delay the input block, and the timer output connected to the input key uppavleniya, characterized in that the outlet is connected to tsifpoanalogovogo Transmitter vto.poy input block selector to the lowest value and the delay the input by the third block.

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