RU1780088C - Computer-to-user interface unit - Google Patents

Abstract

The invention relates to computer technology and can be used in automated control systems, which include computers. The purpose of the invention is to enhance functionality by reducing exchange times. The device comprises computers, subscribers, reconciliation switch, control registers, communication register, reconfiguration registers, OR group of elements, bus drivers, decoders, and communication switch. The introduction of control registers, reconfiguration registers, a group of OR elements, bus formers, decoders, and a switch made it possible to expand the functionality of the device by reducing exchange time. 2 il.fe The invention relates to computer technology and can be used in automated control systems, which include a computer. The aim of the invention is to expand the functionality of the device by reducing exchange time. FIG. 1 shows a functional diagram of the device: in FIG. 2 is a timing diagram. A device for interfacing a computer with subscribers comprises a computer 1. subscriber 2, coordination switch 3, n control registers 4, communication register 5, M reconfiguration registers 6, group of elements 7. bus communication former 8, bus channel shapers 9, write decoder 10, read decoder 11, communication switch 12. Matching switch 3 provides a interface for interfacing with inputs and outputs of subscribers 2. Registers 4, 5, 6 are software accessible for computers. The number of registers 4, 6 is determined by the number of inputs and outputs in subscribers 2. The bit depth of each register is determined by the interface and the type of computer used. Bus drivers 8, 9 can be implemented, for example, on the K 589 series (K589AP16), in this case VK The input of the bus driver 8 is permanently connected to the logical 1 bus (not shown in Fig.). The VK input of each bus driver 9 is individually controlled by a signal from one of the outputs of the OR elements 7 in the process of reading information from subscribers 2, the Decoder 10, using the computer interface signals (write-read, marker) in the information recording mode, converts the specified computer address code of one from registers 4. 5 or 6 to the write strobe, which is with ^ 00о о00 00

Description

the corresponding output of the decoder 10 enters the control input of one of the selected computer registers 4, 5 or 6, and records information in it.

The decoder 11 operates in the mode of reading information from subscribers 2, forming the output of the corresponding computer address, a reading strobe, which through the group of elements OR 7 goes to the VK input of the bus driver 9 and opens the bus driver 9, the address of which is given to the computer,

The communication switch 12 allows the user, by commands from the computer, to carry out any required circuit of each of the inputs of the switch with any of its outputs, i.e. switch 12 is fully accessible.

The connections of the S-inputs and outputs of the switch are described by the following structural matrix

Ci Ci2 ... c ... CiA

C21 C22 ... C ... C2A

Q ii s with LA

- M S. s

b „

where Cij means there is a connection between the 1-input of the switch 12 and its J-output.

The number of rows and columns of the matrix corresponds to the number of inputs and outputs of the switch. The number of inputs and outputs of the switch 12 is determined by the user based on the number of g-inputs and R-outputs in the monitored subscriber 2.

The switch 12 can be implemented, for example, on the basis of the matrix bidirectional switch K1509KP2, which is designed to transmit a digital signal from any of its inputs to any of the outputs.

A timing diagram of the operation of the device is shown in FIG. 2, where the I-V stages of the operation of the device in the write and read modes according to the algorithm described in the description. The algorithm may be different. It depends on the technical capabilities of the computer 1, the control object and the user program;

ЗП / ЧТ, Дзп / Чт, А, М - main computer signals;

10, 11, 4, 6, 3, 5 - signals to you; od; eh of the corresponding devices;

Vzp, 9ht - condition of bus formers, the BC chain is formed. For 8ht, 9zp - AB chain is formed;

d - while providing a communication protocol between the device and the computer 1.

A device for interfacing a computer 1 with bondents works as follows. If it is necessary to write information to one of the registers 4, 5, 6, operations are performed in the following order;

1) the Record signal, which is fed to the input YB of the shaper 8, the computer 1 sets the transmission direction in the shaper 8 from input B to output C; 2) on the data bus through the shaper 8 information from the computer 1 is fed to the inputs of registers 4, 5, 6;

3) Computer 1 sets the address of one of the registers 4, 5 or 6;

4) at the signal of the Marker at the output of the decoder 10, a recording gate appears, according to which information from the computer 1 is recorded 8 selected register 4, 5 or 6;

5) after a time determined by the computer 1, the recording cycle can be repeated.

To transmit information to subscriber 2, which has been previously recorded in one or more registers 4, the following operations are performed. In the computer program 1, the user lays down the order of access to each subscriber 2. For each specific subscriber 2, it is necessary to determine how many inputs and how many outputs, what specific contact numbers.

Based on the information received, it is determined:

- how many registers 4 will be required to be able to simultaneously send signals to all inputs of subscriber 2;

- which shapers 9, respectively associated with the required registers 4, must be switched to transmission mode

information from input A to output B, and which drivers 9 need to be disabled;

- what kind of connection of inputs with outputs must be made in the switch 12, so that through the switch 3 coordination

connected to the outputs of the subscriber 2. Thus, in the mode of transmitting information from the computer 1 to the inputs of the subscriber 2 requires:

1) repeat several times (the number of times depends on the bit of the information word of the computer 1) the recording cycle, fill in the required number of registers 4 with information from the computer 1, which is intended for subsequent simultaneous transmission

to all g-inputs of subscriber 2.

2) make the necessary connections in the switch 12. For this, it is necessary to write codes in the register for reconfiguration with computer 1, with which the inputs of the switch 12 are connected to its required outputs;

3) set with computer 1 subscriber address 2;

4) write the control words from the computer 1 in the register 5, each bit of which is designed to control the shapers 9.

If, for example, zero is written in some bit of register 5; then he. having arrived at the YB input of the corresponding driver 9, it will only switch it to the state of transferring information from input A to output B, and through the group of elements OR 7. Having entered the VK input of the same driver 9, it will allow its operation

If, for example, a unit is written in the bit of register 5, then, having received the YB input of the corresponding driver 9, it will switch it only to the state of transferring information from input B to output C, but through the group of elements OR 7, entering the VK input of this the shaper 9 will prohibit its operation, i.e. output C of driver 9 will have a high output impedance (third state).

. As a result of the operations performed, the outputs of the register 4 simultaneously receive signals at all the g-inputs of subscriber 2. The duration of their exposure is determined by the subscriber 2 verification program, i.e. Until the moment of writing to the registers A of another information.

In response to one, several or all of the R-outputs of subscriber 2, response signals appear that computer 1 can read by performing the following operations:

1) the Read signal, which is fed to the input YB of the shaper 8, the computer 1 sets the transmission direction in the shaper 8 from input A to output B:

2) Computer 1 sets the address of one of the formers 9, through which information from the R-outputs of subscriber 2 will go to the A-input of the former 8. In the recording mode of information, all the former 9 intended for transmission have already been switched, but at the same time via the VK input were put in a third state.

Now, in reading mode, each of these shapers 9 will alternately (according to the program) be opened by a signal from the output of decoder 11. This signal, passing through a group of elements OR 7, will open on the VC input only the required shaper 9.

Thus, it is possible to check the operability of each of subscribers 2. Moreover, if verification of subscribers 2 is not required for all g-inputs and R-outputs, then using the proposed device,

perform checks of subscribers 2 in the full amount of information exchange, as provided in the prototype.

Claims (1)

The claims  A device for interfacing a computer with subscribers, comprising a reconciliation switch, a first control register and a communication register, characterized in that what. In order to expand the functionality by reducing the time of the exchange, it contains n - 1 control registers (where n is the number of subscribers), M reconfiguration registers (where M n - 1), a group of OR elements. bus shaper, p channel shapers, write decoder, read decoder, communication switch, first inputs, which are connected to the first inputs and outputs of the matching switch, the second inputs and outputs of which are inputs and outputs of the device for connecting to inputs subscriber outputs, the second inputs and outputs of the communication switch are connected to the first inputs and outputs of the corresponding bus channel former, the outputs of which are connected to the information inputs of the bus former, input-output which is the input-output device for connection to a computer data bus. the first control input of the write decoder and read decoder is the first input of the device for connecting to the first bit of the computer control bus, the second control input of the write decoder and read decoder is the second input of the device for connecting to the second bit of the computer control bus and is connected to the control input of the bus driver, the first group of outputs of which is connected to the groups of information inputs M reconfiguration registers, the second group of outputs of the bus driver is connected to the group The information inputs of the communication register, the n groups of outputs of the bus communication former are connected to the groups of information inputs of the same control registers, the outputs of the M reconfiguration registers are connected to the control inputs of the communication switch, the address inputs of the device are connected to the bus of the computer address and are connected to the address inputs of the switch matching with the information inputs of the write decoder and the read decoder, the output of the write decoder is connected to the control inputs of the communication register, n control registers, M reg moat reconfiguration decoder reading outputs connected to first inputs of the corresponding element or group, the second inputs of which are connected to respective outputs of the register communication and are connected to the control inputs of the bus drivers n channel outputs or groups of elements are connected to the sample inputs of the bus drivers crystal n channels,