NL8020334A - - Google Patents
Download PDFInfo
- Publication number
- NL8020334A NL8020334A NL8020334A NL8020334A NL8020334A NL 8020334 A NL8020334 A NL 8020334A NL 8020334 A NL8020334 A NL 8020334A NL 8020334 A NL8020334 A NL 8020334A NL 8020334 A NL8020334 A NL 8020334A
- Authority
- NL
- Netherlands
- Prior art keywords
- conductive
- strips
- level
- slices
- substrate
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Dram (AREA)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12091780A | 1980-02-12 | 1980-02-12 | |
US12091780 | 1980-02-12 | ||
US8000662 | 1980-05-22 | ||
PCT/US1980/000662 WO1981002367A1 (fr) | 1980-02-12 | 1980-05-22 | Boitier de micro-plaquettes superposees a double rangee de connexions |
Publications (1)
Publication Number | Publication Date |
---|---|
NL8020334A true NL8020334A (fr) | 1982-01-04 |
Family
ID=22393267
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
NL8020334A NL8020334A (fr) | 1980-02-12 | 1980-05-22 |
Country Status (6)
Country | Link |
---|---|
JP (1) | JPS6356706B2 (fr) |
CA (1) | CA1165465A (fr) |
FR (1) | FR2476389A1 (fr) |
GB (1) | GB2083285B (fr) |
NL (1) | NL8020334A (fr) |
WO (1) | WO1981002367A1 (fr) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58159360A (ja) * | 1982-03-17 | 1983-09-21 | Fujitsu Ltd | 半導体装置 |
US4727410A (en) * | 1983-11-23 | 1988-02-23 | Cabot Technical Ceramics, Inc. | High density integrated circuit package |
JPS61500879A (ja) * | 1983-12-28 | 1986-05-01 | ヒュ−ズ・エアクラフト・カンパニ− | 集積回路メモリ・チップ用フラット・パッケ−ジ |
US4598308A (en) * | 1984-04-02 | 1986-07-01 | Burroughs Corporation | Easily repairable, low cost, high speed electromechanical assembly of integrated circuit die |
US4630096A (en) * | 1984-05-30 | 1986-12-16 | Motorola, Inc. | High density IC module assembly |
US4734315A (en) * | 1985-06-05 | 1988-03-29 | Joyce Florence Space-Bate | Low power circuitry components |
EP0241236A3 (fr) * | 1986-04-11 | 1989-03-08 | AT&T Corp. | Récipient à cavité pour dipositifs à ondes acoustiques de surface et électroniques associées |
GB2199182A (en) * | 1986-12-18 | 1988-06-29 | Marconi Electronic Devices | Multilayer circuit arrangement |
FR2625042B1 (fr) * | 1987-12-22 | 1990-04-20 | Thomson Csf | Structure microelectronique hybride modulaire a haute densite d'integration |
US5150196A (en) * | 1989-07-17 | 1992-09-22 | Hughes Aircraft Company | Hermetic sealing of wafer scale integrated wafer |
FR2772516B1 (fr) * | 1997-12-12 | 2003-07-04 | Ela Medical Sa | Circuit electronique, notamment pour un dispositif medical implantable actif tel qu'un stimulateur ou defibrillateur cardiaque, et son procede de realisation |
GB9915076D0 (en) * | 1999-06-28 | 1999-08-25 | Shen Ming Tung | Integrated circuit packaging structure |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3341649A (en) * | 1964-01-17 | 1967-09-12 | Signetics Corp | Modular package for semiconductor devices |
US3372310A (en) * | 1965-04-30 | 1968-03-05 | Radiation Inc | Universal modular packages for integrated circuits |
US3500440A (en) * | 1968-01-08 | 1970-03-10 | Interamericano Projects Inc | Functional building blocks facilitating mass production of electronic equipment by unskilled labor |
US3555364A (en) * | 1968-01-31 | 1971-01-12 | Drexel Inst Of Technology | Microelectronic modules and assemblies |
JPS5332233B1 (fr) * | 1968-12-25 | 1978-09-07 | ||
US3746934A (en) * | 1971-05-06 | 1973-07-17 | Siemens Ag | Stack arrangement of semiconductor chips |
US3760090A (en) * | 1971-08-19 | 1973-09-18 | Globe Union Inc | Electronic circuit package and method for making same |
US3927815A (en) * | 1971-11-22 | 1975-12-23 | Ngk Insulators Ltd | Method for producing multilayer metallized beryllia ceramics |
US3777220A (en) * | 1972-06-30 | 1973-12-04 | Ibm | Circuit panel and method of construction |
US3777221A (en) * | 1972-12-18 | 1973-12-04 | Ibm | Multi-layer circuit package |
US4012766A (en) * | 1973-08-28 | 1977-03-15 | Western Digital Corporation | Semiconductor package and method of manufacture thereof |
US4038488A (en) * | 1975-05-12 | 1977-07-26 | Cambridge Memories, Inc. | Multilayer ceramic multi-chip, dual in-line packaging assembly |
US4079511A (en) * | 1976-07-30 | 1978-03-21 | Amp Incorporated | Method for packaging hermetically sealed integrated circuit chips on lead frames |
US4224637A (en) * | 1978-08-10 | 1980-09-23 | Minnesota Mining And Manufacturing Company | Leaded mounting and connector unit for an electronic device |
-
1980
- 1980-05-22 WO PCT/US1980/000662 patent/WO1981002367A1/fr active Application Filing
- 1980-05-22 JP JP50202880A patent/JPS6356706B2/ja not_active Expired
- 1980-05-22 GB GB8129603A patent/GB2083285B/en not_active Expired
- 1980-05-22 NL NL8020334A patent/NL8020334A/nl unknown
-
1981
- 1981-02-11 CA CA000370651A patent/CA1165465A/fr not_active Expired
- 1981-02-12 FR FR8102748A patent/FR2476389A1/fr active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS57500220A (fr) | 1982-02-04 |
GB2083285B (en) | 1984-08-15 |
FR2476389A1 (fr) | 1981-08-21 |
JPS6356706B2 (fr) | 1988-11-09 |
GB2083285A (en) | 1982-03-17 |
FR2476389B1 (fr) | 1983-12-16 |
CA1165465A (fr) | 1984-04-10 |
WO1981002367A1 (fr) | 1981-08-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5448511A (en) | Memory stack with an integrated interconnect and mounting structure | |
US5611876A (en) | Method of making a multilayer LTCC tub architecture for hermetically sealing semiconductor die, external electrical access for which is provided by way of sidewall recesses | |
US5379191A (en) | Compact adapter package providing peripheral to area translation for an integrated circuit chip | |
US5289346A (en) | Peripheral to area adapter with protective bumper for an integrated circuit chip | |
US5585675A (en) | Semiconductor die packaging tub having angularly offset pad-to-pad via structure configured to allow three-dimensional stacking and electrical interconnections among multiple identical tubs | |
US5006673A (en) | Fabrication of pad array carriers from a universal interconnect structure | |
US4991000A (en) | Vertically interconnected integrated circuit chip system | |
US4763188A (en) | Packaging system for multiple semiconductor devices | |
US6351880B1 (en) | Method of forming multi-chip module having an integral capacitor element | |
US7045901B2 (en) | Chip-on-chip connection with second chip located in rectangular open window hole in printed circuit board | |
US5600541A (en) | Vertical IC chip stack with discrete chip carriers formed from dielectric tape | |
US5780925A (en) | Lead frame package for electronic devices | |
US5410107A (en) | Multichip module | |
US6552416B1 (en) | Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring | |
US5177863A (en) | Method of forming integrated leadouts for a chip carrier | |
US5654221A (en) | Method for forming semiconductor chip and electronic module with integrated surface interconnects/components | |
US4448306A (en) | Integrated circuit chip carrier | |
JPS6355213B2 (fr) | ||
JPH06216297A (ja) | 介挿体リードフレームを有する回路組立体 | |
JPS63211660A (ja) | 集積回路用高端子数パッケージ | |
EP0509065A1 (fr) | Procede et appareil de production de boitiers de circuits integres de densite ultra-elevee | |
WO1988005251A1 (fr) | Boitier electronique a haute densite comprenant des sous-modules empiles | |
NL8020334A (fr) | ||
KR20130091624A (ko) | 반도체 장치 및 그 제조방법 | |
KR100360077B1 (ko) | 전도성트레이스와리드프레임리드를결합하는고밀도집적회로조립체 |