WO1981002367A1 - Boitier de micro-plaquettes superposees a double rangee de connexions - Google Patents

Boitier de micro-plaquettes superposees a double rangee de connexions Download PDF

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Publication number
WO1981002367A1
WO1981002367A1 PCT/US1980/000662 US8000662W WO8102367A1 WO 1981002367 A1 WO1981002367 A1 WO 1981002367A1 US 8000662 W US8000662 W US 8000662W WO 8102367 A1 WO8102367 A1 WO 8102367A1
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
intra
level
wafers
conductive strips
Prior art date
Application number
PCT/US1980/000662
Other languages
English (en)
Inventor
A Antes
Original Assignee
Mostek Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mostek Corp filed Critical Mostek Corp
Priority to NL8020334A priority Critical patent/NL8020334A/nl
Priority to DE19803050182 priority patent/DE3050182A1/de
Publication of WO1981002367A1 publication Critical patent/WO1981002367A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Definitions

  • the present invention relates generally to electronic packaging, and particularly to inter-layer and intra-layer connecting means for multi-chip modules. Description of the Prior Art:
  • the packaging of electronic equipment has become a major factor in the design and manufacture of contemporary electronic systems. New • packaging techniques are required to meet the demand for reduced physical size and improved reliability at lower cost. The problem of efficient packaging is particularly important in electronic circuits which utilize microcircuit structures of the type implemented by LSI techniques on a semiconductor substrate chip.
  • Conventional electronic circuit packages for semiconductor chips are adapted to enclose and hermetically seal the chip devices, while also providing heat dissipation, structural support, electrical attachment of device leads to external pin connectors, and electrical interconnection with other devices in the package.
  • Such packages are usually formed of one or more layers of a non-conductive substrate wafer, with a central cavity in which the semiconductor chip is received.
  • Flexible metal leads are extended between the layers to the central cavity for connection with the device input/output leads. Because of industry standards relating to the exterior dimensions for electronic circuit packages, including spacing between leads and between lead rows in the case of the standard dual in-line package, the presence of multiple flexible metal leads has limited the number of circuit devices which can be encapsulated in a standard package.
  • RAM random access memory
  • MOS/LSI complementary metal-oxide-semiconductor
  • One particular industry package standard for memory devices specifies 300 mil row spacing with external pins mounted on 100 mil centers in each row. Memory capacity for this standard package can be upgraded from a pair of 8K bit RAM devices, to a pair of 16K bit RAM devices, or to a pair of 64K bit RAM devices.
  • the chip substrate area required to implement the increased memory is also increased, thereby reducing to a minimum the area available for the device lead attachment within a package having standard dimensions. Accordingly, various attempts have been made to redesign the package in order to provide a larger chip cavity. It will be appreciated that the mounting area available for the device substrate, for a given standard package, is necessarily limited by the space required for device lead bonding and by the minimum dimensions necessary to provide a hermetic seaL
  • the conventional dual chip, in-line packaging assembly has resulted because of the memory substrate area constraint and has doubled memory capacity while conforming with lead row standards.
  • the principal object of the present invention is to provide an electronic circuit package having a substantially increased device packaging density which conforms with established standards.
  • a related object is to provide an electronic circuit package for encapsulating and interconnecting multiple semiconductor chips.
  • Another object of the invention is to provide an electronic circuit package for encapsulating and interconnecting four identical semiconductor chips for multiplex operation.
  • Yet another object of the invention is to provide an electronic circuit package for encapsulating and interconnecting multiple pairs of semiconductor circuit devices in an over/under, dual chip in-line arrangement in which each chip device may be operated independently of the other chip devices on a multiplex basis with only a minimum number of external connector pins.
  • a vertically stacked array of substrate wafers which form a support core in which windows are formed for separately receiving and mounting semiconductor chip circuit devices.
  • Device support surfaces and device lead connecting surfaces are exposed by each window on one or more of the substrate wafers.
  • Intra-level conductive strips are separately disposed on each lead connecting surface for attachment to the input/output leads of each semiconductor chip and extend along the interface of one or more superposed pairs of substrate wafers for connection to external connector pins.
  • Inter-level conductive interconnects are embedded in one or more of the substrates for interconnecting the intra-level conductive strips of one substrate level with the intra-level conductive strips of a different level.
  • four identical RAM chips are encapsulated and interconnected for multiplex operation in an over/under, dual in-line arrangement.
  • two RAM chips are mounted in in ⁇ line relation on a common substrate wafer at an upper level, and two RAM chips are mounted on a common substrate wafer at a lower level.
  • Corresponding data and power terminals of the chips on the upper level are interconnected in common with each other and to a common external pin by the combination of intra-level conductive strips extending through the interface of adjacent wafer substrates at first and second levels, and by inter-level conductive interconnects which intersect and are embedded in the substrate wafer on whic the device leads are bonded.
  • Identical power and data terminals of the lowe RAM chips are similarly interconnected with each other and are interconnecte with the corresponding data and power terminals of the upper RAM chips by a intermediate group of intra-level conductive strips and by inter-leve conductive interconnects which intersect the substrate wafers which form th interface along which the intermediate group of intra-level conductive strip are disposed.
  • FIGURE 1 is an assembled perspective view of an over/under, dua chip in-line electronic circuit package of the present invention
  • FIGURE 2 is a perspective view of the package assembly shown i FIGURE 1 with the hermetic sealing lids removed;
  • FIGURE 3 is an exploded perspective view of the multiple chi packaging assembly shown in FIGURE 1;
  • FIGURE 4 is a bottom plan view of a vertically stacked array o substrate wafers which form a support core;
  • FIGURE 5 is a sectional view of the support core taken along th lines V-V of FIGURE 4;
  • FIGURE 6 is a partial sectional view which illustrates an example o device lead bonding, intra-level and inter-level conductive interconnect layout;
  • FIGURE 7 is an exploded view of the wafer support core whic illustrates the various levels of conductive interconnect strips
  • FIGURES 8 - 12 are plan views of metalization deposits which for the intra-level conductive strips and the inter-level conductive interconnects and,
  • FIGURE 13 is a block diagram which identifies the function of eac external pin of the package shown in FIGURE 1.
  • RAM random access memory
  • the packaging assembly of the invention may be used to encapsulate and interconnect discrete as well as integrated circuit devices but has particular utility for integrated circuits having multiple input/output leads. Accordingly, it should be understood that the invention may be incorporated in any modular structure housing two or more circuit devices. Furthermore, the invention may be used to interconnect active or passive substrate devices having a variety of circuit elements, including but not limited to discrete, micro-discrete and integrated circuit components, and hybrid combinations of discrete and integrated devices.
  • the package assembly 10 includes a composite core 12 which is intersected by four device cavities 14, 16, 18 and 20.
  • the cavities are sealed by metal lids 22, 24 which are aligned with the top and bottom of the core and are sealed at both top and bottom by running the assembly through a standard sealing form.
  • the sealing procedure is carried out in an atmosphere of nitrogen.
  • the lids are bonded to the top and bottom of the core at the interface of a solder preform 25 on the inside of each lid and conductive metalization deposits 26, 28 along the top and bottom sealing surfaces of the core.
  • the core is punched, metalized and sintered to form a dense, multilayer ceramic core.
  • ceramic raw materials may be used, for example, alumina, zircon, aluminum silicates, titanium dioxide, or berylia ceramic.
  • the core 12 is formed by a vertically stacked array of six ceramic substrate wafers, beginning with an uppermost wafer 30, intermediate wafers 32, 34, 36, 38, and a lowermost wafer 40. These ceramic layers are sintered to produce a monolithic core structure.
  • the layers are elongated ceramic wafers having a length of approximately 1.1 inches in length, 0.29 inches in width, and 0.015 inch in thickness.
  • the metalization deposits 26, 28 are preferably an alloy of tungsten, nickel and gold.
  • the package assembly 10 is an over/under, dual chip in-line arrangement having twenty-two external connector pins 42 arranged in two parallel rows along the longitudinal edges of the package.
  • the connector pin rows are laterally spaced along a 300 mil row center, according to industry standards. Additionally, adjacent pins 42 in each row are spaced relative to each other on 100 mil centers.
  • the connector pins 42 preferably comprise a forty-two percent nickel iron alloy. It will be appreciated that during assembly, the connector pins 42 are structurally interconnected by a connecting band (not shown) integral with the pins, preferably stamped from the same metal sheet. In most instances, the connecting bands remain attached to the connector pins for handling purposes only and are severed prior to ultimate use.
  • each ceramic wafer Prior to assembly, each ceramic wafer is punched to form cavities and vertical interconnect openings and is then metalized to form the hermetic sealing deposits 26, 28 and to form intra-level conductive strips and inter-level conductive interconnects for interconnecting circuit devices received within the cavities.
  • each chip includes identical input/output leads 46 which are interconnected with each other and with the external connector pins 42 to permit the RAM memory chips to be operated on a multiplex basis. Although each chip includes sixteen input/output leads, all four RAM memory devices may be operated on a time sharing, multiplex basis through only twenty-two external connector pins 42. According to this arrangement, a 256K RAM is implemented in the same package type as previously used for 16K and 64K RAM memory packages, without changing package width. This is achieved by combining four 64K RAM chips 44A, 44B, 44C and 44D in the single package assembly 10. To remain within the established standard length constraints, two
  • RAM chips, 44A and 44B were mounted in the top cavities and two RAM chips
  • 44C and 44D were mounted in the bottom cavities in an over/under, dual chip in-line configuration. This unique packaging approach permits four separate memory devices to be mounted within a single standard package.
  • each conductive bonding pad 48 preferably comprises a composite conductive strip of tungsten applied by a silk screen printing process, followed by a plated deposit of nickel, with a plated gold overlay.
  • the multi-chip package assembly 10 is a multiple cavity package with the top and next adjacent substrate layers 30, 32 having coincident window openings 50, 52, respectively, which in combination define the device cavity 14.
  • Coincident window openings 54, 56 are likewise formed in the upper substrate wafers 30, 32 and in combination define the cavity 16.
  • Coincident window openings 58, 60 and 62, 64 formed in the lower substrate wafers 38, 40 define the lower device cavities 18, 20, respectively.
  • the window openings 58, 60 and 62, 64 which make up the device cavities 18, 20 are rectangular, concentric openings with the outermost openings 60, 64 being relatively larger than the coincident interior window openings 58, 62, respectively.
  • annular device lead connecting surfaces 66, 68 are exposed around the border of the relatively smaller openings 58, 64, respectively.
  • the lead connecting surfaces 66, 68 each form a part of the under side of the substrate wafer 38 which overlies the lowermost bottom substrate wafer 40.
  • Similar annular lead connecting surfaces 70, 72 are exposed on the upper side of the uppermost intermediate substrate wafer 32.
  • intra-level conductive strips 74 extend across the surfaces of the intermediate wafer substrates 32, 34, 36 and 38.
  • the intra-level conductive strips 74 are deposited in an intricate pattern as can best be seen in FIGURES 8 - 12. According to a predetermined interconnection plan, selected ones of the intra-level conductive strips 74 extend from the bonding pads 48 along the interface of adjacent substrate wafers to the edge of the wafer on which they are deposited for connection to an external connector pin 42.
  • Certain ones of the intra-level conductive strips extend from bonding pads across the surface of the substrate wafer and terminate at a conductive inter-level interconnect 78 for connection to an intra-level conductive strip 74 on the surface of an underlying substrate wafer.
  • the intra-level conductive strips 74 preferably comprise tungsten and are silk screen printed onto the wafer surface according to conventional printing techniques. According to this interconnection arrangement, corresponding pins of each RAM chip 44A, 44B, 44C and 44D, which are functionally equivalent, are interconnected to each other, and to a common external connector pin 42.
  • device lead No. 2 of each RAM chip which is the DATA INPUT terminal, is interconnected with all other DATA INPUT terminals No. 2 by means of intra-level conductor strips 74, 76 and inter-level conductive interconnects 78 which are deposited on or embedded in the intermediate substrate wafers 32, 34, 36 and 38.
  • This interconnection of multiple devices is made possible by the provision of the intermediate substrate wafer 34, both sides of which have intra-level conductive strips 74, 76.
  • the wafer 34 is intersected by inter-level connective interconnects 78 which connect intra-level strips of two different levels.
  • the intermediate substrate wafer 34 serves not only to interconnect both of the RAM chips in the upper in-line cavities 14, 16, but simultaneously interconnects the RAM chips 44C, 44D in the lower in-line cavities 18, 20, and further simultaneously connects predetermined ones of the device terminals having a common function to a common external connector pin 42.
  • the provision of the intermediate substrate wafer having intra-level conductive strips on both sides as well as inter-level conductive interconnects makes possible both horizontal and vertical interconnection of all circuit devices and external connector pins.
  • each RAM chip includes an internal ground terminal, designated "G", and a package grounding pad 88 which is directly bonded to the underlying ground strip.
  • the ground strips are all interconnected by vertically aligned inter-level conductive interconnects 90 which are embedded in a central location in each substrate wafer.
  • the intermediate substrate wafers 34, 36 simultaneously provide a
  • each device row address strobe RAS and column address strobe CAS terminals of each device are maintained separate with respect to each other, each being connected to a separate external connector pin. This allows each RAM chip to be selected and used on a time sharing, multiplex basis. Therefore only twenty-two pins are needed to operate four RAM chips, each having sixteen input/output terminals.
  • the multiple intra-level conductive strip arrangement in combination with the inter-level conductive interconnects, provides pattern flexibility for arranging the bond pads for attachment to the device input/ output leads. Additionally, the device substrate area is not compromised, nor is the hermetic seal surface area reduced by this arrangement. Consequently, the bonding pads need not be offset or staggered with respect to each other, thereby making possible the simultaneous, direct bonding of the device input/output leads to the bonding pads in an automatic bonding operation. Thus the device density of the package is substantially increased from two devices to four devices, without compromising device substrate area or sealing surface requirements, and also conforming with packaging dimensions established by industry standards.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Dram (AREA)

Abstract

Boitier (10) de circuit electronique servant a encapsuler et interconnecter deux ou plusieurs micro-plaquettes de semi-conducteurs (44A). Un reseau empile verticalement de tranches de substrat forme un noyau de support (12) dans lequel sont amenagees des fenetres (14, 16, 18, 20) destinees a recevoir les microplaquettes. Des surfaces de support du dispositif et des surfaces (70, 72) de connexion des fils du dispositif sont exposees par chaque cavite sur une ou plusieurs des tranches du substrat. Des bandes conductrices intermediaires (74) sont deposees separement sur chaque surface de connexion de fil de maniere a etre fixees au fil (42) d'entree/sortie des dispositifs du circuit et s'etendent le long de l'interface d'une ou plusieurs paires superposees de tranches de substrat pour etre connectees aux broches de connexion exterieures. Des interconnexions (78) conductrices intermediaires sont noyees dans un ou plusieurs substrats de maniere a interconnecter les bandes conductrices intermediaires d'un niveau de substrat avec les bandes conductrices intermediaires d'un niveau different. Dans un mode de realisation preferentiel, quatre micro-plaquettes (RAM) identiques sont encapsulees et interconnectees pour un fonctionnement multiplexe dans une disposition superposee a double rangee de connexions.
PCT/US1980/000662 1980-02-12 1980-05-22 Boitier de micro-plaquettes superposees a double rangee de connexions WO1981002367A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
NL8020334A NL8020334A (fr) 1980-02-12 1980-05-22
DE19803050182 DE3050182A1 (de) 1980-02-12 1980-05-22 Over/under dual in-line chip package

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12091780A 1980-02-12 1980-02-12
US120917 1980-02-12

Publications (1)

Publication Number Publication Date
WO1981002367A1 true WO1981002367A1 (fr) 1981-08-20

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PCT/US1980/000662 WO1981002367A1 (fr) 1980-02-12 1980-05-22 Boitier de micro-plaquettes superposees a double rangee de connexions

Country Status (6)

Country Link
JP (1) JPS6356706B2 (fr)
CA (1) CA1165465A (fr)
FR (1) FR2476389A1 (fr)
GB (1) GB2083285B (fr)
NL (1) NL8020334A (fr)
WO (1) WO1981002367A1 (fr)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0089248A2 (fr) * 1982-03-17 1983-09-21 Fujitsu Limited Assemblage dense d'empaquetages de pinces semi-conductrices
WO1985005733A1 (fr) * 1984-05-30 1985-12-19 Motorola, Inc. Assemblage de modules a circuit integre de densite elevee
US4598308A (en) * 1984-04-02 1986-07-01 Burroughs Corporation Easily repairable, low cost, high speed electromechanical assembly of integrated circuit die
EP0204568A2 (fr) * 1985-06-05 1986-12-10 Harry Arthur Hele Spence-Bate Composants de circuits à basse puissance
EP0241236A2 (fr) * 1986-04-11 1987-10-14 AT&T Corp. Récipient à cavité pour dipositifs à ondes acoustiques de surface et électroniques associées
AU568416B2 (en) * 1983-12-28 1987-12-24 Raytheon Company Flat package for integrated circuit memory chips
US4727410A (en) * 1983-11-23 1988-02-23 Cabot Technical Ceramics, Inc. High density integrated circuit package
EP0272046A2 (fr) * 1986-12-18 1988-06-22 Marconi Electronic Devices Limited Structure de circuit comprenant un substrat composite en céramique
FR2625042A1 (fr) * 1987-12-22 1989-06-23 Thomson Csf Structure microelectronique hybride modulaire a haute densite d'integration
US5150196A (en) * 1989-07-17 1992-09-22 Hughes Aircraft Company Hermetic sealing of wafer scale integrated wafer
EP0923130A1 (fr) * 1997-12-12 1999-06-16 ELA MEDICAL (Société anonyme) Circuit électronique, notamment pour un dispositif médical implantable actif tel qu'un stimulateur ou défibrillateur cardiaque, et son procédé de réalisation

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9915076D0 (en) * 1999-06-28 1999-08-25 Shen Ming Tung Integrated circuit packaging structure

Citations (12)

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US3341649A (en) * 1964-01-17 1967-09-12 Signetics Corp Modular package for semiconductor devices
US3372310A (en) * 1965-04-30 1968-03-05 Radiation Inc Universal modular packages for integrated circuits
US3500440A (en) * 1968-01-08 1970-03-10 Interamericano Projects Inc Functional building blocks facilitating mass production of electronic equipment by unskilled labor
US3555364A (en) * 1968-01-31 1971-01-12 Drexel Inst Of Technology Microelectronic modules and assemblies
US3760090A (en) * 1971-08-19 1973-09-18 Globe Union Inc Electronic circuit package and method for making same
US3777221A (en) * 1972-12-18 1973-12-04 Ibm Multi-layer circuit package
US3777220A (en) * 1972-06-30 1973-12-04 Ibm Circuit panel and method of construction
US3927815A (en) * 1971-11-22 1975-12-23 Ngk Insulators Ltd Method for producing multilayer metallized beryllia ceramics
US4012766A (en) * 1973-08-28 1977-03-15 Western Digital Corporation Semiconductor package and method of manufacture thereof
US4038488A (en) * 1975-05-12 1977-07-26 Cambridge Memories, Inc. Multilayer ceramic multi-chip, dual in-line packaging assembly
US4079511A (en) * 1976-07-30 1978-03-21 Amp Incorporated Method for packaging hermetically sealed integrated circuit chips on lead frames
US4224637A (en) * 1978-08-10 1980-09-23 Minnesota Mining And Manufacturing Company Leaded mounting and connector unit for an electronic device

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Publication number Priority date Publication date Assignee Title
JPS5332233B1 (fr) * 1968-12-25 1978-09-07
US3746934A (en) * 1971-05-06 1973-07-17 Siemens Ag Stack arrangement of semiconductor chips

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3341649A (en) * 1964-01-17 1967-09-12 Signetics Corp Modular package for semiconductor devices
US3372310A (en) * 1965-04-30 1968-03-05 Radiation Inc Universal modular packages for integrated circuits
US3500440A (en) * 1968-01-08 1970-03-10 Interamericano Projects Inc Functional building blocks facilitating mass production of electronic equipment by unskilled labor
US3555364A (en) * 1968-01-31 1971-01-12 Drexel Inst Of Technology Microelectronic modules and assemblies
US3760090A (en) * 1971-08-19 1973-09-18 Globe Union Inc Electronic circuit package and method for making same
US3927815A (en) * 1971-11-22 1975-12-23 Ngk Insulators Ltd Method for producing multilayer metallized beryllia ceramics
US3777220A (en) * 1972-06-30 1973-12-04 Ibm Circuit panel and method of construction
US3777221A (en) * 1972-12-18 1973-12-04 Ibm Multi-layer circuit package
US4012766A (en) * 1973-08-28 1977-03-15 Western Digital Corporation Semiconductor package and method of manufacture thereof
US4038488A (en) * 1975-05-12 1977-07-26 Cambridge Memories, Inc. Multilayer ceramic multi-chip, dual in-line packaging assembly
US4079511A (en) * 1976-07-30 1978-03-21 Amp Incorporated Method for packaging hermetically sealed integrated circuit chips on lead frames
US4224637A (en) * 1978-08-10 1980-09-23 Minnesota Mining And Manufacturing Company Leaded mounting and connector unit for an electronic device

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0089248A3 (en) * 1982-03-17 1985-12-18 Fujitsu Limited Dense mounting of semiconductor chip packages
EP0089248A2 (fr) * 1982-03-17 1983-09-21 Fujitsu Limited Assemblage dense d'empaquetages de pinces semi-conductrices
US4727410A (en) * 1983-11-23 1988-02-23 Cabot Technical Ceramics, Inc. High density integrated circuit package
AU568416B2 (en) * 1983-12-28 1987-12-24 Raytheon Company Flat package for integrated circuit memory chips
EP0167538B1 (fr) * 1983-12-28 1989-01-18 Hughes Aircraft Company Boitier plat pour puces de memoires a circuits integres
US4598308A (en) * 1984-04-02 1986-07-01 Burroughs Corporation Easily repairable, low cost, high speed electromechanical assembly of integrated circuit die
WO1985005733A1 (fr) * 1984-05-30 1985-12-19 Motorola, Inc. Assemblage de modules a circuit integre de densite elevee
EP0204568A3 (fr) * 1985-06-05 1988-07-27 Harry Arthur Hele Spence-Bate Composants de circuits à basse puissance
EP0204568A2 (fr) * 1985-06-05 1986-12-10 Harry Arthur Hele Spence-Bate Composants de circuits à basse puissance
EP0241236A3 (fr) * 1986-04-11 1989-03-08 AT&T Corp. Récipient à cavité pour dipositifs à ondes acoustiques de surface et électroniques associées
EP0241236A2 (fr) * 1986-04-11 1987-10-14 AT&T Corp. Récipient à cavité pour dipositifs à ondes acoustiques de surface et électroniques associées
EP0272046A3 (fr) * 1986-12-18 1988-09-28 Marconi Electronic Devices Limited Structure de circuit comprenant un substrat composite en céramique
EP0272046A2 (fr) * 1986-12-18 1988-06-22 Marconi Electronic Devices Limited Structure de circuit comprenant un substrat composite en céramique
FR2625042A1 (fr) * 1987-12-22 1989-06-23 Thomson Csf Structure microelectronique hybride modulaire a haute densite d'integration
EP0325068A1 (fr) * 1987-12-22 1989-07-26 Thomson-Csf Structure microélectronique hybride modulaire à haute densité d'intégration
US4958258A (en) * 1987-12-22 1990-09-18 Thomson-Csf Modular hybrid microelectronic structures with high density of integration
US5150196A (en) * 1989-07-17 1992-09-22 Hughes Aircraft Company Hermetic sealing of wafer scale integrated wafer
EP0923130A1 (fr) * 1997-12-12 1999-06-16 ELA MEDICAL (Société anonyme) Circuit électronique, notamment pour un dispositif médical implantable actif tel qu'un stimulateur ou défibrillateur cardiaque, et son procédé de réalisation

Also Published As

Publication number Publication date
GB2083285B (en) 1984-08-15
FR2476389B1 (fr) 1983-12-16
CA1165465A (fr) 1984-04-10
GB2083285A (en) 1982-03-17
FR2476389A1 (fr) 1981-08-21
NL8020334A (fr) 1982-01-04
JPS57500220A (fr) 1982-02-04
JPS6356706B2 (fr) 1988-11-09

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