NL8020334A - - Google Patents

Description

80 2 0 3 3 br1- N.O. 30281 1 TWO-LAYER CHIP HOUSING LINED ABOVE / UNDER ...... ..... | I! PLACED CHIPS.

I! BACKGROUND OF THE INVENTION. ! ; Field of the invention: j

The present invention generally relates to electronic housings, and more particularly relates to 5; intermediate layers and inner layer positioned connecting means for j i; 1 modules with multiple chips.

Description of the prior art:

The packaging of electronic equipment has become an important factor in the design and manufacture of contemporary electronic systems. New packaging techniques are needed to comply j: i

the demand for reduced physical dimensions and improved occupancy i fidelity at lower costs. The problem of efficient processing I

packing is particularly important in electronic circuits, which use microcircuit structures of the type implemented by LSI techniques on a semiconductor substrate chip.

Conventional electronic circuit housings for semiconductor i i chips are adapted to enclose the chip devices and hermetically | j, while also providing heat dissipation, structural support, electrical connection of the installation pipes to | I: \ 20 external connector pins, and electrical connections to other devices! in the housing. Such housings are on usual | formed from one or more layers of a non-conductive substrate ; slice with a central cavity in which the semiconductor chip is received.

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: Flexible metal pipes run between the layers to the central cavity for connections to the input / output pipes of the device | : ting. Due to the industry standards related to the | external dimensions of electronic circuit housings, including of the distance between the pipes and between the rows of pipe | in the case of standard enclosures with double interconnection ! i i 30: line located contact rows, has the presence of several flexible! ! "I | metal pipes the number of circuit devices, which in a standard; housing can be encapsulated, limited.

! There is a continuing interest in enlarging the device! | housing density, especially for semiconductor memory j 135 i circuits used in high speed data processing circuits, for example random access memory circuits j i (RAM) implemented by MOS / LSI techniques on semiconductor substrate | potato chips. A particular industry enclosure standard for memory devices 8 02 0 3 3 4 2: specifies a 300 mil row spacing with external con-; ! tact pens with centers at 100 mil apart in each row. j | The memory capacity for this standard enclosure can be increased from a pair of 8 Kbit RAM devices to a pair of 16 Kbit RAM devices or up to a pair of 64 Kbit RAM devices.

! | : As the memory capacity of the chips increases, so does! the substrate surface required for the implementation of the enlarged area. ! memory, leaving the area available for confirmation of | I [I! the installation pipes in a housing with standard dimensions up to | 10; a minimum is reduced. Therefore, various attempts have been made to redesign the housing to provide a larger chip cavity. It will be understood that the mounting area for that

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The device substrate available for a given standard housing is necessarily limited by the space required for attachment of the device lines and by the minimum dimensions required to provide a hermetic seal. De: conventional dual chip housing with aligned contacts j | has been recovered therefrom, due to the limitation on memory substrate surface [; results and has doubled memory capacity while meeting the standards for the line rows. Although the memory capacity can be increased by further memory chips in tandem, in the; Aligned relationship with the standard dual aligned chip configuration, adding such configurations, due to the established standards for the spacing between the conductor centers and the maximum number of external pins and the housing length, do not have widespread acceptance achieved. Therefore, there exists a | | serious and continuing need for an improved electronic circuit housing in which the device density can become significant i! I magnify while meeting established industry housing 30! standards.

i! ! i; | | BRIEF DESCRIPTION OF THE OBJECTS OF THE INVENTION The main object of the present invention is i; half to provide an electronic circuit pack with one; 35j considerably increased device packing density, which is satisfactory! | ! i to established standards.

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A related object is to provide an electronic circuit package for encapsulating and interconnecting multiple semiconductor chips. ; Another object of the invention is to provide 8 02 0 3 3 4 3 an electronic circuit pack for encapsulation and interconnection. connecting four identical semiconductor chips for plywood operation.

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Yet another object of the invention is to provide an electronic circuit package for encapsulating and interconnecting multiple pairs of semiconductor circuit devices in a dual aligned chip configuration with chips placed at the top and bottom, each chip device independent of the others. Ii: chip devices can be operated on a multiplex basis with only; a minimum number of external connector pins.

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BRIEF DESCRIPTION OF THE INVENTION

The above objectives have been achieved by a vertical stacked array of substrate wafers, which form a support core in which windows are formed for separately receiving and mounting semiconductor circuit device chips. Device bearing surfaces and connection surfaces for the device pipes are exposed! ; laid through each window on one or more of the substrate slabs. Conductive j; the intermediate level strips are mounted separately on each conductor ; connecting surface for attachment to the input / output lines j 20 of each semiconductor chip and extending along the connection; | plane of one or more superimposed pairs of substrate slices; for connection to external connector pins. Conductive intermediate level-I i! ! compounds are embedded in one or more of the substrates to form the jelly. | connect the inner level strips of one substrate level to i 25 | the conductive inner level strips of another level. ! ! In a preferred embodiment, four identical RAM chips are in; i: encapsulated and interconnected for multiplex operation in two! ''; well aligned configuration with top and bottom positions. In this con! ; figuration, two RAM chips are mounted in line with el- i I! I 30; card on a common substrate slice on an upper level and two! | RAM chips are mounted on a common substrate slice on! i a lower level. Corresponding data and power connections of [: i the upper level chips are jointly connected to each other; and with a common external pin through the combination of jelly-35 | th inner level strips extending through the interface of [the adjacent substrate slabs on first and second levels and through | conductive intermediate level connections that cut and embed the substrate wafer to which the device leads are attached.

: Identical power and data connections of the lower RAM chips 40 are similarly interconnected and connected 802 03 3 4

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4 to the corresponding data and power terminals of the upper RAM chips through an intermediate group of conductive inner level strips and through conductive intermediate level connections connecting the substrate i '; slices defining the interface along which the intermediate group I 5; of conductive inner level strips, cut.

The new features that characterize the invention have been defined. nited by the appended claims. The foregoing and other objects, advantages and features of the invention will become apparent in the following and for the purpose of illustrating the invention; 10, but not limited thereto, as an example, an embodiment of the invention is shown in the appended drawing.

| ; BRIEF DESCRIPTION OF THE DRAWING

i 1 'j j! FIGURE 1 is a composite perspective view of an electronic circuit housing with a dual aligned configuration of; top and bottom chips according to the invention; FIGURE 2 shows a perspective view of the housing assembly shown in FIGURE 1 with the hermetic seal covers removed; j: 20 FIGURE 3 shows an exploded perspective view of the j | ; multiple chip housing assembly shown in FIGURE 1; ! | FIGURE 4 shows a planar bottom view of a vertical stacked array of substrate wafers forming a support core; FIGURE 5 shows a sectional view of the support core along the 25I line V-V in FIGURE 4; FIGURE 6 shows a partial cross section illustrating an example II; j i of a configuration with device line attachment, conductive bond! n level and intermediate level connections; FIGURE 7 shows an exploded view of the adhesive support core showing the various levels of conductive bonding. i j | I illustrates comics; FIGURES 8-12 show planar views of metalization precipitation; j i gen which the conductive inner level strips and conductive intermediate level! form strips; and, ! 35: FIGURE 13 shows a block diagram showing the function of each of the: j; external pins of the housing shown in FIGURE 1 has been identified. ji DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 40 In the description that follows, the invention has been described in combination with random access memory circuit devices (RAM), j | I implemented by MOS / LSI techniques on 8 0 2 0 3 "3 5 I" It will be understood, however, that the housing composition of the invention can be used to encapsulate and interconnect both discrete and integrated circuit devices, but is particularly useful for integrated circuits with multiple circuits. input / output lines It will therefore be understood that the invention may be embodied in any modular structure housing two or more circuit devices. Furthermore, the invention may be used to interconnect of active or passive substrate devices with a variety of circuit elements, including only none t limited to discrete, micro-dis-! crete and integrated circuit components, and hybrid combinations of I>! : discrete and integrated devices.

! 15 The same parts are in the description and in the drawings! ! ; marked with the same respective reference numbers. Figures j: i of the drawing are not necessarily to scale and in some! In cases, parts have been enlarged to more clearly indicate certain features of the invention. With reference to the drawings, in particular in FIGS. 1, 2 and 3, a multilayer ceramic multi-chip housing composition 10 having a dual aligned configuration of chips in top / bottom conforms to the teachings. of the | ; invention illustrated. The housing assembly 10 is provided with I 25 | a composite core 12 intersected by four device! cavities 14, 16, 18 and 20. The cavities are sealed by metal lids ; 22, 24 aligned with the top and bottom of the i ί; core and sealed are both top and bottom 1 8020334 through the composition by a standard sealing method. The af-; (i 130; sealing process is carried out in a nitrogen atmosphere. The cover is bonded to the top and bottom of the core with 1 pre-formed solder interlayer 25 on the inside of each cover and conductive metallization deposits 26, 28 along the top and bottom I 'sealing surfaces of the core.

| 35; The core is perforated, metallized and sintered to form a | form a dense multilayer ceramic core. A wide variety! starting ceramic materials can be used, for example aluminum, zirconium, aluminum silicates, titanium dioxide or berylium; ramik. With the exception of the covers 22, 24, the core 12 is formed •! | 40i from a vertically stacked array of six ceramic substrate slabs, 1 6! I starting with the top slice 30, the intermediate slices 32, 34, j! , 36, 38 and a bottom slab 40. These ceramic layers are sintered to produce a monolithic core structure. The layers consist of elongated ceramic slabs approximately 1 cm in length ; j 5i 1.1 inches, a width of 0.29 inches and a thickness of 0.015 inches. The me- | tallization precipitates 26, 28 are preferably of an alloy of wool frame, nickel and gold. j | The housing assembly 10 is a dual aligned connector : figuration with chips in top / bottom provided with twenty two i

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10 external connector pins 42 arranged in two parallel rows along the longitudinal edges of the housing. The connector pin rows are spaced laterally with 300 mils between centers ! ! of the rows, in accordance with industry standards. Moreover! ! 1 | the adjacent pins 42 in each row are spaced apart with a spacing of 100 mils between the centers of the pins. nen. The connector pins 42 preferably consist of a 42% nickel i

iron alloy. It will be clear that during assembly the I

Connector pins 42 are structurally connected to a connector band (not shown) integrally formed with the pins, preferably I20; is punched from the same metal sheet. In most cases, the connection bands attached to the connection pins are left alone! treatment purposes and are separated prior to final use.

Before assembly, each ceramic slab is die-cut to form the cavities and vertical connection openings and then metallized to form the hermetic seal deposits | ! 26, 28 and the conductive inner leve strips and conductive! "; intermediate level links to form the circuit devices that | | be received in the cavity to be connected »!

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i 30! As best seen in Figures 2 and 3, identical ones!

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Semiconductor RAM chips 44A, 44B, 44C and 44D received in the device cavities. Each chip includes identical input / output lines 46, which are interconnected and connected to the external connector pins 42 so that it is possible to operate the RAM memory chips I35 on a multiplex basis. Although each chip is equipped with | : sixteen input / output lines can all four RAM memory-; ; Timed and multiplexed directions are operated through only twenty two external connector pins 42. According to this configuration, a 256 K RAM is implemented in the same enclosure previously used for 5 K 1 for 16 K and 64 K RAM memory enclosures, without the 8 02 0 3 3 4 7 I width of the housing has been changed. This has been achieved by four 64 K i! | RAM chips 44A, 44B, 44C and 44D to be combined in the single housing assembly 10. In order to remain within the established standard length limits, two RAM chips 44A and 44B are mounted in the upper cavity! 5; two RAM chips 44C and 44D are mounted in the lower cavities in i: i ί; a dual-aligned chip configuration with top and bottom 1: j went. This unique approach to the housing makes it possible to; mount four separate memory devices in a single stand; earth housing.

| In order to minimize the loss of yield due to defective RAM chips, the RAM chips are completely burned, tested and adjusted at speed before being disassembled in the housing composition! transferred. The RAM chips are preferably mounted on one of one

; patterned dielectric / conductor band composition, and after 1

15 testing separately from the tape to produce input / output lines 46j of the device having a predetermined length and a; array pattern compatible with the auto-bonding method: she. The conduits 46 are attached to the conductive attachment island : 48. Each conductive attachment island 48 preferably consists of one; 20 Tungsten composite conductive strip applied by a silk screen printing process followed by a plated nickel deposit with a plated gold top layer.

The multi-chip housing assembly 10 is a multi-housing ! further cavities with the upper substrate layer 30 and the subsequent substrate layer Substrate layer 32 coinciding respective window openings 50, 52; : | ; which together define the device cavity 14. Similarly; Coincidentally, window openings 54, 56 are formed in the top window substrate slabs 30, 32 and in combination they define the hollow at 16. Coincident window openings 58, 60 and 62, 64 are 30 respectively! also formed in the bottom substrate wafers 38, 40 to define the bottom device cavities 18, 20.

It will now be seen from FIGURE 4 that the window openings 58, 60 and 62, 64 forming the device cavities 18, 20 are rectangular, concentric openings with the outer openings 60, 64 growing proportionally. ; j35 are then the coincident inner respective window openings 5, 58, 62. This configuration exposes annular device guides abutment surfaces 66, 68 around the edge of the relatively narrower openings 58, 64, respectively. make the; conductor bonding surfaces 66, 68 each part of the bottom side! 40 of the substrate wafer 38 overlying the bottom bottom substrate wafer 8020334 1: 40. Similar annular conductor bonding surfaces 70, 72; lie boat at the top of the upper intermediate substrate: slice 32.

From FIGURES 7 and 8-12 it now appears that conductive intermediate level-5; strips 74 extend over the surfaces of the intermediate substrate wafers 32, 34, 36 and 38. The conductive intermediate level strips | 74 are deposited in an intricate pattern as best seen: is shown in FIGS. 8-12. According to a predetermined connection plan, selected copies of the conductive intermediate level strips j | i j 10I 74 from the attachment islands 48 along the interface of the attachment j

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| ; adjacent substrate slices to the edge of the slice on which they are i; | 1; knocked down to be connected to an external connector pin 42.

Certain specimens of the conductive intermediate level strips, designated I, the strips 76 extend from the attachment islands across 15 | the surface of the substrate wafer and terminate at a conductive bond i | nen level connection 78 for connection with a conductive intermediate level j! : strip 74 on the surface of an underlying substrate slice.

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The intermediate conductive level strips 74 preferably consist of tungsten and are printed on the wafer surface by a silk screen method in accordance with conventional printing techniques. According to j | :! this connection configuration becomes corresponding pins of each j RAM chip 44A, 44B, 44C and 44D, which are functionally equivalent, with

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i connected together and connected with a common external project; nector pin 42. The device line No. 2 of each RAM chip, which is the I 25 DATA INPUT terminal, is connected, for example, to all other DATA INPUT terminals No. 2 through intermediate level conductor j-strips 74, 76 and conductive inner level connections 78 deposited on or embedded in the intermediate substrate wafers 32, 34, 36 and 38.

30 | This connection of the multiple devices has been made possible] | by applying the intermediate substrate wafer 34, of which j • I! ! | Both sides are provided with conductive intermediate level strips 74, 76.! j: The slice 34 is intersected by conductive inner level connections 78 j: connecting the intermediate level strips of two different levels *! I35! to connect. Thus, the intermediate substrate wafer 34 does not only do I: i; service for connecting both RAM chips in the top aligned j! cavities 14, 16, but at the same time connects the RAM chips 44C, 44D in the lower aligned cavities 18, 20 and at the same time connects prej | except certain instances of the device terminals with a common function with a common external connectors 1 «0X0X3 4 ~ 9 I 42. The presence of the intermediate substrate wafer with conductive intermediate level strips on both sides as well as conductive inner ni! | Level connections allows both horizontal and vertical interconnection of all circuit devices and the external connector pins: 5 pins.

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t In addition, the internal circuit connections between the device are 1; i; ! markings, such as the common ground terminal, provided by the: conductive ground strips 80, 82 and 84, 86. As shown in the figures; 6, 8 and 12, each RAM chip is provided with an internal earth connection, I 10; marked "G", and a housing grounding island 88, which is direct; | ) is attached to the underlying ground strip. The earth strips are al-

all interconnected by the vertically aligned conductive I.

inner level connections 90, which are embedded in a central location in

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i each substrate slice. j; At the same time, the intermediate substrate wafers 34, 36 provide a structural mounting base for each chip, while the top and bottom chips are spaced from each other. isolated. The application of these two intermediate substrate wafers also allows printing of the conductive intermediate level strips on the i i j; 20 top and bottom sides of the wafer 34, which is the key to the horizontal and vertical interconnections thereby coupling the common input / output terminals of all four RAM chips.

It is noted that the row address release line RAS and the; ! , 25; column address release line CAS of each device must be separated! \ hold relative to each other and each are connected to a community ! reasonable external connector pin. That allows every j | RAM chip is selected and used on a time division / multiplex • b; ! j sis. Therefore, only twenty two pins are required to operate four RAM chips 301 each with sixteen input / output terminals.

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The multiple conductive intermediate level strip configuration, in conjunction with the conductive inner level joints, provides a pattern flexibility for arranging the bonding islands for attachment. i | establishment of the entrance / exit pipes of the establishment. Furthermore, 35; there is no compromise on the device substrate surface, j i nor is the hermetic sealing surface area reduced by j; ί: this configuration. As a result, the attachment islands need not be shifted or stepped relative to each other; placed in a way that allows a simultaneous | 40 direct connection of the input / output lines of the device 8 0 2 0 3 3 4 10 I I to the attachment countries to be carried out in an automatic attachment! testing operation. The device tightness of the housing has increased considerably from two devices to four devices without compromising the device substrate area or the sealing surface requirements, while also meeting the housing dimensions! i j i to established Industry Standards.

While a particular embodiment of the invention has been illustrated and described in detail, it will be appreciated that various modifications can be made without departing from the spirit and scope of the invention.

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Claims (10)

1. Electronic circuit housing for encapsulating circuit devices: each provided with input / output lines, which housing; zing is provided with a vertically stacked array of substrate wafer features defining a support core, which support core has recesses that cut one or more of said substrate wafers to receive the circuit devices separately; device support surfaces i t I l and device lead connection surfaces are exposed on one or | ; more of said substrate wafers; conductive intermediate level strips 10. are arranged separately on each conductor connecting surface for j | attachment to the input / output lines of one of the circuitinj; directions; conductive intermediate level strips of each group expire I I along the interface of one or more superimposed pairs of I substrate wafers for connection to external connector pins; and 15 conductive inner level means are embedded in one or more of the areas. mentioned substrates for interconnecting the conductive intermediate level strips of one level with the conductive intermediate level strips of different level. The electronic circuit housing as defined in claim 1; 20 wherein said support core is provided with at least one intermediate wafer with conductive intermediate level strips deposited on both of its inserts. I i sides and at least one conductive inner level connection configuration embedded in the intermediate slab for connecting | an intermediate level strip on one side with an intermediate level strip on the opposite side of the intermediate slab. Electronic circuit housing as defined in claim 1, | said support core comprising at least two device cavities placed vertically one above the other relative to each other within the aforementioned. the array and at least one intermediate substrate slice applied between -30! The aforementioned device cavities. The electronic circuit housing as defined in claim 1, ί I wherein said support core is provided with six rectangular slabs ί! ; which includes an upper pair of slices, a lower pair of slices, and j; | an intermediate pair of slices sandwiched between the top and bottom j35 | pairs of slices, with the top and bottom pair slices each | are provided with coincident window openings defining the device cavities. i 5. Electronic circuit housing for encapsulating first | and second circuit devices each including input / output conductor; i i j 40 i, which packaging is provided with a vertically stacked array! i: 1020334 V; of substrate slices, which stacked array includes:! a top slab with a window opening; a bottom slab with a window opening; intermediate adhesives introduced between the top and bottom Third slices, which intermediate adhesives are top and bottom; side surfaces coincide with the respective top and bottom window openings, and the top and bottom side surfaces ί i; ; each device support surfaces and device guide attachment surfaces i 1 '| surfaces accessible through the respective window openings! 10: ten; ! i "; first and second groups of conductive intermediate level strips applied to the upper and lower respective device guides; der attachment surfaces, for mounting the input / output I! conductors of the first and second circuit devices, respectively: i 15; conductive strips of each group extending at least partially over the top and bottom side surfaces of the intermediate adhesives along the interface of the interposed one! stick to the peripheral edge of the interposed adhesives to be coupled with external connecting pins. | I 20 | The electronic circuit housing as defined in claim 5, comprising conductive inner level means embedded in said I j intermediate adhesives about a conductive intermediate level strip of the i 1 j; connect the upper group to a conductive intermediate level strip of the i; bottom group. j; i j 7. Electronic circuit housing for encapsulating first and second circuit devices each with input / output lines, which | enclosure includes a vertically stacked array of substrate j; slabs, which stacked array includes: an upper slab with first and second spaced window openings I30; in an aligned relationship; ; a bottom slab with an internal side surface located below the I; first and second window openings, the side surfaces of the jI; i i | said bottom slice coincide with the first and second window options and each have device support areas and device 35! conductor support surfaces accessible via the respective! window openings; and, ! first and second groups of conductive strips applied to the | first and second respective device conductor attachment surfaces for mounting the input / output conductors of the first and second circuit devices, respectively, with conductive 8020334 V I strips of each group extending at least in part; the inner surface of the bottom slab along the | top and bottom slabs to the peripheral edge of the bottom slab to be connected with external connecting pins. 5 i 8. Electronic circuit housing for encapsulating first and second circuit devices each with input / output conductors, which housing is provided with a vertically stacked array of substrate slices, which includes stacked array: | a top pair of superimposed slices each with bottom! 10 overlapping surfaces and coincident window openings; i a bottom pair of superimposed slices each with un- I. "Overlapping surfaces and coincident window openings; j where the coincident window openings of each pair of top j; j i define lower cavities for receiving the first and second circuit devices, respectively, and the window; Opening of the outer slice of each pair at least partially covered! 1 is slid with respect to the inner window opening of each adhesive cavity exposing at least a portion of the adhesive surface surrounding the inner window opening and respective upper ones. 20 and lower device guide attachment surfaces are defined; intermediate adhesives sandwiched between the upper and lower adhesive pairs to provide a support base for said | circuit devices; [; : 2. first and second groups of conductive strips applied to the! upper and lower respective device guide attachment | surfaces for attachment to the input / output conductors of the I! ; I first and second circuit devices, respectively, and expired at least in part over the wafer in which the inner window is formed. 30. along the interface of the overlapping wafer surfaces to a peripheral edge of the inner wafer of each respective wafer pair for connection to an external connector pin. \ The electronic circuit housing as defined in claim 8, j wherein the intermediate adhesives comprise first and second at el- | ; j. 35. slices placed one of these intermediate slices being provided with conductive intermediate level strips on both sides and | the other intermediate slab is provided with conductive intermediate level; strips on one side only facing one of the cavities, and: provided with at least one conductive inner level connection configuration [40. tie embedded in each intermediate wafer for connecting intermediate level strips with intermediate level strips of a transport | peeling level. 10. Dual aligned multiple chips in top / bottom module containing the combination of: \ 5: a vertically stacked array of substrate slices defining a support core, which support core is provided with first sate and second intermediate | horizontal slices sandwiched between top and bottom slices, yes! each core has first and second cavities containing one or more of the said; intersecting higher level slabs and third and fourth cavities intersecting one or more of said lower level wafers exposing device support surfaces and conductor bonding surfaces on said intermediate wafers; | attachment islands deposited on the conductor connection I I i surfaces in each cavity; j] 15j receive a semiconductor chip device with input / output conductors in each cavity, each chip device being mounted on j: the support surface and the input / output conductors of each device; are paired with the attachment islands in each cavity; j! external connector pins fitted in first and second parallel! 2. rows along opposite sides of said array; conductive intermediate level strips individually mounted on each conductive connection surface with one end electrical; coupled to one of said attachment islands and the opposite end is electrically coupled to one of the gears; 25 mentioned external connector pins, and one of said intermediate: wafer includes conductive intermediate level strips applied to both of its internal sides, and the other intermediate wafer; equipped with conductive intermediate level strips on only a few! side facing one of said cavity pairs; 30. Include at least one conductive interior level connection configuration: prayer in each slab with conductive intermediate level strips for electrically interconnecting conductive intermediate level strips of one; level with conductive intermediate level strips of a different level, j35; where functionally equivalent terminals of all four j; chips are connected together and with a common | I; reasonable external connector pin allowing operation of the devices on a time division / plywood basis via a minimum number of external connector pins. ί i 8020334 V Ir SUMMARY OF PUBLICATION j [; j An electronic circuit housing (10) for encapsulation and de- | The interconnection of two or more semiconductor chips (44A) has been disclosed. A vertically stacked array of substrate slices forms a | 5; support core (12) in which windows (14, 16, 18, 20) are formed for decompression; capture of the chip. Device support surfaces and device guides; the bonding surfaces (70, 72) are exposed in each well on one or more of the substrate wafers. The conductive intermediate level strips (74) are deposited separately on each conductor connecting surface 10: just for attachment to the input / output conductors (42) of the circuit devices and extend along the interface of one or; more superimposed pairs of substrate slices for compound j! with external connector pins. Conductive inner level connection configuration; Rations (78) are embedded in one or more of the substrates for bonding the conductive intermediate level strips of one substrate level with conductive intermediate level strips of different levels. ! ! In a preferred embodiment, four identical RAM chips are encapsulated and interconnected for a multiplex operation in duplicate! Aligned top / bottom configuration. i 20 ******************** I j; I; :; i "! I i; j i; i 1 | ! | ! i i; j I -; I. ; ί! ! i: 8020334