NL188315C - Geintegreerde halfgeleiderschakeling en werkwijze voor het vervaardigen van een geintegreerde halfgeleiderschakeling. - Google Patents

Geintegreerde halfgeleiderschakeling en werkwijze voor het vervaardigen van een geintegreerde halfgeleiderschakeling.

Info

Publication number
NL188315C
NL188315C NLAANVRAGE8103986,A NL8103986A NL188315C NL 188315 C NL188315 C NL 188315C NL 8103986 A NL8103986 A NL 8103986A NL 188315 C NL188315 C NL 188315C
Authority
NL
Netherlands
Prior art keywords
semiconductor circuit
integrated semiconductor
manufacturing
integrated
circuit
Prior art date
Application number
NLAANVRAGE8103986,A
Other languages
English (en)
Other versions
NL188315B (nl
NL8103986A (nl
Original Assignee
Tokyo Shibaura Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co filed Critical Tokyo Shibaura Electric Co
Publication of NL8103986A publication Critical patent/NL8103986A/nl
Publication of NL188315B publication Critical patent/NL188315B/nl
Application granted granted Critical
Publication of NL188315C publication Critical patent/NL188315C/nl

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
NLAANVRAGE8103986,A 1980-08-29 1981-08-27 Geintegreerde halfgeleiderschakeling en werkwijze voor het vervaardigen van een geintegreerde halfgeleiderschakeling. NL188315C (nl)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP55119294A JPS5743438A (en) 1980-08-29 1980-08-29 Semiconductor device and manufacture thereof
JP11929480 1980-08-29

Publications (3)

Publication Number Publication Date
NL8103986A NL8103986A (nl) 1982-03-16
NL188315B NL188315B (nl) 1991-12-16
NL188315C true NL188315C (nl) 1992-05-18

Family

ID=14757841

Family Applications (1)

Application Number Title Priority Date Filing Date
NLAANVRAGE8103986,A NL188315C (nl) 1980-08-29 1981-08-27 Geintegreerde halfgeleiderschakeling en werkwijze voor het vervaardigen van een geintegreerde halfgeleiderschakeling.

Country Status (4)

Country Link
US (1) US4551743A (nl)
JP (1) JPS5743438A (nl)
DE (1) DE3134110A1 (nl)
NL (1) NL188315C (nl)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6072243A (ja) * 1983-09-28 1985-04-24 Matsushita Electric Ind Co Ltd 半導体集積回路装置
FR2554638A1 (fr) * 1983-11-04 1985-05-10 Efcis Procede de fabrication de structures integrees de silicium sur ilots isoles du substrat
JPH0779133B2 (ja) * 1986-06-12 1995-08-23 松下電器産業株式会社 半導体装置の製造方法
USRE33622E (en) * 1986-09-04 1991-06-25 At&T Bell Laboratories Integrated circuits having stepped dielectric regions
DE3809218C2 (de) * 1987-03-20 1994-09-01 Mitsubishi Electric Corp Halbleitereinrichtung mit einem Graben und Verfahren zum Herstellen einer solchen Halbleitereinrichtung
US5306940A (en) * 1990-10-22 1994-04-26 Nec Corporation Semiconductor device including a locos type field oxide film and a U trench penetrating the locos film
KR950000103B1 (ko) * 1991-04-15 1995-01-09 금성일렉트론 주식회사 반도체 장치 및 그 제조방법
KR100213189B1 (ko) * 1992-06-11 1999-08-02 김광호 반도체메모리장치 및 그 제조방법
JPH06132392A (ja) * 1992-06-23 1994-05-13 Nec Corp 半導体装置
JP3396553B2 (ja) * 1994-02-04 2003-04-14 三菱電機株式会社 半導体装置の製造方法及び半導体装置
JP3360970B2 (ja) * 1995-05-22 2003-01-07 株式会社東芝 半導体装置の製造方法
US6110798A (en) 1996-01-05 2000-08-29 Micron Technology, Inc. Method of fabricating an isolation structure on a semiconductor substrate
US6465865B1 (en) * 1996-01-05 2002-10-15 Micron Technology, Inc. Isolated structure and method of fabricating such a structure on a substrate
US5963789A (en) * 1996-07-08 1999-10-05 Kabushiki Kaisha Toshiba Method for silicon island formation
US6765280B1 (en) * 1998-12-21 2004-07-20 Agilent Technologies, Inc. Local oxidation of a sidewall sealed shallow trench for providing isolation between devices of a substrate
WO2001043186A1 (en) * 1999-12-13 2001-06-14 Infineon Technologies North America Corp. Body contacted silicon-on-insulator (soi) structure and method of fabrication
US6853048B1 (en) 2000-08-11 2005-02-08 Agere Systems Inc. Bipolar transistor having an isolation structure located under the base, emitter and collector and a method of manufacture thereof
US6864547B2 (en) 2001-06-15 2005-03-08 Agere Systems Inc. Semiconductor device having a ghost source/drain region and a method of manufacture therefor
US6958518B2 (en) * 2001-06-15 2005-10-25 Agere Systems Inc. Semiconductor device having at least one source/drain region formed on an isolation region and a method of manufacture therefor
US6784076B2 (en) * 2002-04-08 2004-08-31 Micron Technology, Inc. Process for making a silicon-on-insulator ledge by implanting ions from silicon source
US6809386B2 (en) * 2002-08-29 2004-10-26 Micron Technology, Inc. Cascode I/O driver with improved ESD operation
KR100525797B1 (ko) * 2003-06-18 2005-11-02 동부아남반도체 주식회사 소자분리막 구조 및 제조 방법
KR100487657B1 (ko) * 2003-08-13 2005-05-03 삼성전자주식회사 리세스된 게이트를 갖는 모스 트렌지스터 및 그의 제조방법
US20070059897A1 (en) * 2005-09-09 2007-03-15 Armin Tilke Isolation for semiconductor devices
US20070224775A1 (en) * 2006-03-27 2007-09-27 Nick Lindert Trench isolation structure having an expanded portion thereof
FR2914491A1 (fr) * 2007-03-27 2008-10-03 Commissariat Energie Atomique Procede de fabrication de zones actives de germanium sur isolant avec tranchees fines d'isolation laterale a bords arrondis.
US7692483B2 (en) * 2007-10-10 2010-04-06 Atmel Corporation Apparatus and method for preventing snap back in integrated circuits
US8085604B2 (en) * 2008-12-12 2011-12-27 Atmel Corporation Snap-back tolerant integrated circuits
US9536999B2 (en) 2014-09-08 2017-01-03 Infineon Technologies Ag Semiconductor device with control structure including buried portions and method of manufacturing
US9935126B2 (en) * 2014-09-08 2018-04-03 Infineon Technologies Ag Method of forming a semiconductor substrate with buried cavities and dielectric support structures

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1461943A (en) * 1973-02-21 1977-01-19 Raytheon Co Semi-conductor devices
FR2228299B1 (nl) * 1973-05-04 1977-09-02 Radiotechnique Compelec
US4019248A (en) * 1974-06-04 1977-04-26 Texas Instruments Incorporated High voltage junction semiconductor device fabrication
JPS5221782A (en) * 1975-08-13 1977-02-18 Toshiba Corp Producing system and unit of semiconductor
JPS5318384A (en) * 1976-08-04 1978-02-20 Shinkawa Seisakusho Kk Apparatus for wireebonding
US4187125A (en) * 1976-12-27 1980-02-05 Raytheon Company Method for manufacturing semiconductor structures by anisotropic and isotropic etching
US4264382A (en) * 1978-05-25 1981-04-28 International Business Machines Corporation Method for making a lateral PNP or NPN with a high gain utilizing reactive ion etching of buried high conductivity regions
US4196440A (en) * 1978-05-25 1980-04-01 International Business Machines Corporation Lateral PNP or NPN with a high gain
US4209349A (en) * 1978-11-03 1980-06-24 International Business Machines Corporation Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching
JPS56103446A (en) * 1980-01-22 1981-08-18 Fujitsu Ltd Semiconductor device
US4318751A (en) * 1980-03-13 1982-03-09 International Business Machines Corporation Self-aligned process for providing an improved high performance bipolar transistor
JPS56140642A (en) * 1980-04-01 1981-11-04 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPS5712533A (en) * 1980-06-26 1982-01-22 Fujitsu Ltd Manufacture of semiconductor device

Also Published As

Publication number Publication date
DE3134110A1 (de) 1982-04-08
US4551743A (en) 1985-11-05
JPS5743438A (en) 1982-03-11
JPH0158661B2 (nl) 1989-12-13
NL188315B (nl) 1991-12-16
NL8103986A (nl) 1982-03-16
DE3134110C2 (nl) 1989-06-15

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Legal Events

Date Code Title Description
A1A A request for search or an international-type search has been filed
BB A search report has been drawn up
A85 Still pending on 85-01-01
BC A request for examination has been filed
V1 Lapsed because of non-payment of the annual fee

Effective date: 19980301