NL1021337A1 - Uitgangsbuffercircuit voor het reduceren van een variatie in een zwenksnelheid als gevolg van een variatie in een PVT en een belastingscapaciteit van een uitgangsaansluiting, en halfgeleiderinrichting omvattende een dergelijk buffercircuit. - Google Patents

Uitgangsbuffercircuit voor het reduceren van een variatie in een zwenksnelheid als gevolg van een variatie in een PVT en een belastingscapaciteit van een uitgangsaansluiting, en halfgeleiderinrichting omvattende een dergelijk buffercircuit.

Info

Publication number
NL1021337A1
NL1021337A1 NL1021337A NL1021337A NL1021337A1 NL 1021337 A1 NL1021337 A1 NL 1021337A1 NL 1021337 A NL1021337 A NL 1021337A NL 1021337 A NL1021337 A NL 1021337A NL 1021337 A1 NL1021337 A1 NL 1021337A1
Authority
NL
Netherlands
Prior art keywords
variation
buffer circuit
pvt
reducing
semiconductor device
Prior art date
Application number
NL1021337A
Other languages
English (en)
Other versions
NL1021337C2 (nl
Inventor
Soon-Kyun Shin
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of NL1021337A1 publication Critical patent/NL1021337A1/nl
Application granted granted Critical
Publication of NL1021337C2 publication Critical patent/NL1021337C2/nl

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
    • H03K2005/00032—Dc control of switching transistors
    • H03K2005/00039—Dc control of switching transistors having four transistors serially

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
NL1021337A 2001-08-31 2002-08-27 Uitgangsbuffercircuit voor het reduceren van een variatie in een zwenksnelheid als gevolg van een variatie in een PVT en een belastingscapaciteit van een uitgangsaansluiting, en halfgeleiderinrichting omvattende een dergelijk buffercircuit. NL1021337C2 (nl)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2001-0053271A KR100438773B1 (ko) 2001-08-31 2001-08-31 Ｐｖｔ 변화와 출력단자의 부하 커패시턴스의 변화에기인하는 슬루율 변화를 감소시키는 출력버퍼 회로 및이를 구비하는 반도체장치
KR20010053271 2001-08-31

Publications (2)

Publication Number Publication Date
NL1021337A1 true NL1021337A1 (nl) 2003-03-03
NL1021337C2 NL1021337C2 (nl) 2004-05-24

Family

ID=19713796

Family Applications (1)

Application Number Title Priority Date Filing Date
NL1021337A NL1021337C2 (nl) 2001-08-31 2002-08-27 Uitgangsbuffercircuit voor het reduceren van een variatie in een zwenksnelheid als gevolg van een variatie in een PVT en een belastingscapaciteit van een uitgangsaansluiting, en halfgeleiderinrichting omvattende een dergelijk buffercircuit.

Country Status (4)

Country Link
US (1) US6646483B2 (nl)
JP (1) JP3872405B2 (nl)
KR (1) KR100438773B1 (nl)
NL (1) NL1021337C2 (nl)

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KR100505645B1 (ko) * 2002-10-17 2005-08-03 삼성전자주식회사 동작주파수 정보 또는 카스 레이턴시 정보에 따라출력신호의 슬루율을 조절 할 수 있는 출력 드라이버
US7202702B2 (en) * 2003-12-10 2007-04-10 Hewlett-Packard Development Company, L.P. Output buffer slew rate control using clock signal
KR100582359B1 (ko) * 2004-03-03 2006-05-22 주식회사 하이닉스반도체 슬루 레이트가 제어된 반도체 소자의 출력 드라이버
KR101024333B1 (ko) * 2004-05-06 2011-03-23 매그나칩 반도체 유한회사 데이터 출력버퍼
US7157932B2 (en) 2004-11-30 2007-01-02 Agere Systems Inc. Adjusting settings of an I/O circuit for process, voltage, and/or temperature variations
US7425849B2 (en) * 2004-12-31 2008-09-16 Stmicroelectronics Pvt. Ltd. Low noise output buffer capable of operating at high speeds
KR100593451B1 (ko) * 2005-01-07 2006-06-28 삼성전자주식회사 데이터 출력 드라이버 및 이를 구비한 반도체 메모리 장치
KR100670685B1 (ko) * 2005-03-31 2007-01-17 주식회사 하이닉스반도체 반도체 소자의 출력 드라이버
US7495465B2 (en) * 2005-07-22 2009-02-24 Freescale Semiconductor, Inc. PVT variation detection and compensation circuit
JP5025172B2 (ja) * 2005-09-28 2012-09-12 エスケーハイニックス株式会社 スルー−レートが制御されたオープン−ループ出力ドライバー
US7498844B2 (en) * 2005-09-29 2009-03-03 Hynix Semiconductor Inc. Output driver for dynamic random access memory
US7372291B2 (en) * 2005-09-30 2008-05-13 Stmicroelectronics Asia Pacific Pte. Ltd. Circuits having precision voltage clamping levels and method
KR100668498B1 (ko) * 2005-11-09 2007-01-12 주식회사 하이닉스반도체 반도체 메모리의 데이터 출력장치 및 방법
US7464346B2 (en) * 2006-06-20 2008-12-09 Taiwan Semiconductor Manufacturing Co., Ltd. Method for designing phase-lock loop circuits
US7579861B2 (en) 2006-10-02 2009-08-25 Hynix Semiconductor Inc. Impedance-controlled pseudo-open drain output driver circuit and method for driving the same
US7432730B2 (en) * 2007-01-09 2008-10-07 International Business Machines Corporation Time based driver output transition (slew) rate compensation
US8115508B2 (en) * 2007-01-09 2012-02-14 International Business Machines Corporation Structure for time based driver output transition (slew) rate compensation
KR100855274B1 (ko) * 2007-03-30 2008-09-01 주식회사 하이닉스반도체 유닛 딜레이 셀 및 이를 포함하는 지연 고정 루프
KR100890386B1 (ko) * 2007-06-26 2009-03-25 주식회사 하이닉스반도체 데이터 출력장치 및 이를 포함하는 반도체 메모리장치
KR100890384B1 (ko) * 2007-12-26 2009-03-25 주식회사 하이닉스반도체 온도에 따라 슬루율을 조절하는 반도체장치 및 이의 데이터출력방법
KR20090074427A (ko) * 2008-01-02 2009-07-07 삼성전자주식회사 데이터 출력 버퍼 회로 및 그것을 포함하는 반도체 메모리장치
US7764554B2 (en) 2008-03-03 2010-07-27 Micron Technology, Inc. I/O circuit with phase mixer for slew rate control
US7969217B2 (en) * 2009-10-13 2011-06-28 Himax Technologies Limited Output buffer with slew-rate enhancement output stage
JP5331730B2 (ja) * 2010-02-24 2013-10-30 日立オートモティブシステムズ株式会社 内燃機関制御装置
US8768679B2 (en) * 2010-09-30 2014-07-01 International Business Machines Corporation System and method for efficient modeling of NPskew effects on static timing tests
US8519761B1 (en) 2012-05-25 2013-08-27 International Business Machines Corporation Closed-loop slew-rate control for phase interpolator optimization
US8686776B2 (en) 2012-07-24 2014-04-01 International Business Machines Corporation Phase rotator based on voltage referencing
US8638149B1 (en) 2012-08-06 2014-01-28 International Business Machines Corporation Equalized rise and fall slew rates for a buffer
JP6195393B1 (ja) * 2016-03-23 2017-09-13 ウィンボンド エレクトロニクス コーポレーション 出力回路
JP6743095B2 (ja) * 2018-07-24 2020-08-19 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． オフチップドライバ
US10777234B2 (en) 2018-08-29 2020-09-15 Winbond Electronics Corp. Off-chip driver
US10756709B1 (en) * 2019-06-12 2020-08-25 Cirrus Logic, Inc. Controlling edge rate of a switched output stage based on a measured physical quantity

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JPH11250656A (ja) * 1998-03-04 1999-09-17 Hitachi Ltd 半導体集積回路装置
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Also Published As

Publication number Publication date
JP3872405B2 (ja) 2007-01-24
KR100438773B1 (ko) 2004-07-05
US20030042953A1 (en) 2003-03-06
US6646483B2 (en) 2003-11-11
KR20030018742A (ko) 2003-03-06
JP2003179480A (ja) 2003-06-27
NL1021337C2 (nl) 2004-05-24

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RD2N Patents in respect of which a decision has been taken or a report has been made (novelty report)

Effective date: 20040319

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MM Lapsed because of non-payment of the annual fee

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