MY194185A - Method of manufacturing plating films - Google Patents

Method of manufacturing plating films

Info

Publication number
MY194185A
MY194185A MYPI2014001378A MYPI2014001378A MY194185A MY 194185 A MY194185 A MY 194185A MY PI2014001378 A MYPI2014001378 A MY PI2014001378A MY PI2014001378 A MYPI2014001378 A MY PI2014001378A MY 194185 A MY194185 A MY 194185A
Authority
MY
Malaysia
Prior art keywords
main surface
power source
workpiece
current power
direct current
Prior art date
Application number
MYPI2014001378A
Other languages
English (en)
Inventor
Kure Muneaki
Aruga Yosuke
Original Assignee
Shinko Electric Ind Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Ind Co filed Critical Shinko Electric Ind Co
Publication of MY194185A publication Critical patent/MY194185A/en

Links

Classifications

    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/18Electroplating using modulated, pulsed or reversing current
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/007Current directing devices
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/60Electroplating characterised by the structure or texture of the layers
    • C25D5/605Surface topography of the layers, e.g. rough, dendritic or nodular layers
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/60Electroplating characterised by the structure or texture of the layers
    • C25D5/605Surface topography of the layers, e.g. rough, dendritic or nodular layers
    • C25D5/611Smooth layers
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/627Electroplating characterised by the visual appearance of the layers, e.g. colour, brightness or mat appearance
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49579Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582Metallic layers on lead frames

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Lead Frames For Integrated Circuits (AREA)
MYPI2014001378A 2013-05-14 2014-05-12 Method of manufacturing plating films MY194185A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013102470A JP6093646B2 (ja) 2013-05-14 2013-05-14 めっき膜の製造方法

Publications (1)

Publication Number Publication Date
MY194185A true MY194185A (en) 2022-11-17

Family

ID=51878578

Family Applications (1)

Application Number Title Priority Date Filing Date
MYPI2014001378A MY194185A (en) 2013-05-14 2014-05-12 Method of manufacturing plating films

Country Status (5)

Country Link
JP (1) JP6093646B2 (ja)
KR (1) KR102102263B1 (ja)
CN (1) CN104152959B (ja)
MY (1) MY194185A (ja)
TW (1) TWI627315B (ja)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6685112B2 (ja) * 2015-11-18 2020-04-22 株式会社三井ハイテック リードフレーム及びリードフレームパッケージ、並びにこれらの製造方法
JP6905031B2 (ja) * 2016-02-17 2021-07-21 株式会社三井ハイテック リードフレーム及び半導体パッケージ
JP6621681B2 (ja) * 2016-02-17 2019-12-18 株式会社三井ハイテック リードフレーム及びその製造方法、並びに半導体パッケージ
JP6782116B2 (ja) * 2016-08-02 2020-11-11 古河電気工業株式会社 銀被覆材料
CN109468670B (zh) * 2018-11-16 2021-03-26 中山品高电子材料有限公司 引线框架电镀铜层的方法
CN112331566A (zh) * 2020-11-02 2021-02-05 昆山一鼎工业科技有限公司 引线框架表面粗糙度的制造设备及制造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6179988B1 (en) * 1997-08-29 2001-01-30 Electrocopper Products Limited Process for making copper wire
JP3690603B2 (ja) * 2002-11-28 2005-08-31 株式会社中央製作所 連続式めっきの電流制御方法
CN2587889Y (zh) * 2002-12-11 2003-11-26 吕明 制造高孔隙率金属带材的电沉积设备
JP2005097721A (ja) * 2003-08-27 2005-04-14 Yamaha Corp 両面メッキ装置および両面メッキ方法
CN2712947Y (zh) * 2004-07-20 2005-07-27 戴其金 一种双阳极电镀槽
JP4981488B2 (ja) * 2007-03-09 2012-07-18 古河電気工業株式会社 粗化圧延銅板およびその製造方法
KR20100066988A (ko) * 2008-12-10 2010-06-18 삼성테크윈 주식회사 전자회로기판의 균일 도금 방법
KR100950442B1 (ko) * 2009-05-13 2010-04-02 주식회사 모아기술 고주파펄스를 이용한 알루미늄소재의 항균성 표면처리방법
CN102337578B (zh) * 2010-07-19 2014-04-02 北大方正集团有限公司 一种双面电镀槽、板件及电镀方法

Also Published As

Publication number Publication date
TW201500599A (zh) 2015-01-01
JP2014221941A (ja) 2014-11-27
KR20140135108A (ko) 2014-11-25
TWI627315B (zh) 2018-06-21
CN104152959B (zh) 2018-11-13
KR102102263B1 (ko) 2020-04-20
CN104152959A (zh) 2014-11-19
JP6093646B2 (ja) 2017-03-08

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