TW201613033A - Memory structure and manufacturing method therefor - Google Patents

Memory structure and manufacturing method therefor

Info

Publication number
TW201613033A
TW201613033A TW103132085A TW103132085A TW201613033A TW 201613033 A TW201613033 A TW 201613033A TW 103132085 A TW103132085 A TW 103132085A TW 103132085 A TW103132085 A TW 103132085A TW 201613033 A TW201613033 A TW 201613033A
Authority
TW
Taiwan
Prior art keywords
memory structure
portions
manufacturing
method therefor
trenched gate
Prior art date
Application number
TW103132085A
Other languages
Chinese (zh)
Other versions
TWI549225B (en
Inventor
Tzung-Han Lee
Neng-Tai Shih
Yaw-Wen Hu
Cheng-En Lue
Original Assignee
Inotera Memories Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inotera Memories Inc filed Critical Inotera Memories Inc
Priority to TW103132085A priority Critical patent/TWI549225B/en
Priority to CN201410514448.5A priority patent/CN105529330B/en
Publication of TW201613033A publication Critical patent/TW201613033A/en
Application granted granted Critical
Publication of TWI549225B publication Critical patent/TWI549225B/en

Links

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)

Abstract

A memory structure includes a substrate that has a discontinuous well region, a trenched gate, a first doping region, and a second doping region. The first doping region and a second doping region are respectively disposed at two sides of the trenched gate in the substrate. The discontinuous well region includes at least one first portion and at least two second portions, where the first portion and the second portions are not in contact with one another. The first portion is disposed below the trenched gate, and the two second portions are disposed respectively below the portions of the substrate at two sides of the trenched gate.
TW103132085A 2014-09-17 2014-09-17 Memory structure and manufacturing method therefor TWI549225B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW103132085A TWI549225B (en) 2014-09-17 2014-09-17 Memory structure and manufacturing method therefor
CN201410514448.5A CN105529330B (en) 2014-09-17 2014-09-29 memory structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW103132085A TWI549225B (en) 2014-09-17 2014-09-17 Memory structure and manufacturing method therefor

Publications (2)

Publication Number Publication Date
TW201613033A true TW201613033A (en) 2016-04-01
TWI549225B TWI549225B (en) 2016-09-11

Family

ID=55771451

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103132085A TWI549225B (en) 2014-09-17 2014-09-17 Memory structure and manufacturing method therefor

Country Status (2)

Country Link
CN (1) CN105529330B (en)
TW (1) TWI549225B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108346665B (en) * 2017-01-23 2021-03-09 联华电子股份有限公司 Semiconductor element and manufacturing method thereof
CN109037225B (en) * 2018-09-19 2023-09-12 长江存储科技有限责任公司 memory structure

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100382236C (en) * 2005-04-18 2008-04-16 力晶半导体股份有限公司 Production of semiconductor for preventing from being brokendown
KR101934037B1 (en) * 2012-11-21 2018-12-31 삼성전자주식회사 Semiconductor device having supporter and method of forming the same

Also Published As

Publication number Publication date
TWI549225B (en) 2016-09-11
CN105529330B (en) 2019-01-01
CN105529330A (en) 2016-04-27

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