MX9802332A - Operacion y mantenimiento de las redes de distribucion de reloj que tienen redundancia. - Google Patents
Operacion y mantenimiento de las redes de distribucion de reloj que tienen redundancia.Info
- Publication number
- MX9802332A MX9802332A MX9802332A MX9802332A MX9802332A MX 9802332 A MX9802332 A MX 9802332A MX 9802332 A MX9802332 A MX 9802332A MX 9802332 A MX9802332 A MX 9802332A MX 9802332 A MX9802332 A MX 9802332A
- Authority
- MX
- Mexico
- Prior art keywords
- independently
- clsy
- station
- clock
- clock signals
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0421—Circuit arrangements therefor
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0614—Systems characterised by the synchronising information used the synchronising signal being characterised by the amplitude, duration or polarity
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
- H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Small-Scale Networks (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Time-Division Multiplex Systems (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
Abstract
En una red, tal como un conmutador de telecomunicacion grande, destinado para el procesamiento de informacion en diferentes estaciones y para transmitir la informacion entre las estaciones, se proporcionan circuitos (1) que generan señales de reloj compuestas independientemente (CLSY-A, CLSY-B, CLSY-C) que contienen tanto un régimen o ritmo de sincronizacion (CLock) como un régimen o ritmo de sincronizacion de cuadro (SYnch). Estas señales de reloj son transmitidas en tres líneas de transmision diferentes en paralelo independientemente hacia una estacion (II), en donde se hace cierta clase de procesamiento de informacion (4) en los planos redundantes (a, B, C). En la estacion (II) todas las señales de reloj de entrada son alimentadas a cada una de las tres unidades selectoras que funcionan independientemente (3) en donde se hace una seleccion de una señal de reloj para obtener una señal de reloj que va a usarse en los tres planos redundantes (A, B, C), colocados en paralelo uno con respecto al otro, y que funcionan en la estacion, independientemente uno del otro.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE9503371A SE506739C2 (sv) | 1995-09-29 | 1995-09-29 | Drift och underhåll av klockdistributionsnät med redundans |
Publications (1)
Publication Number | Publication Date |
---|---|
MX9802332A true MX9802332A (es) | 1998-08-30 |
Family
ID=20399634
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
MX9802332A MX9802332A (es) | 1995-09-29 | 1998-03-25 | Operacion y mantenimiento de las redes de distribucion de reloj que tienen redundancia. |
Country Status (12)
Country | Link |
---|---|
US (1) | US6195758B1 (es) |
EP (1) | EP0852860A1 (es) |
JP (1) | JPH11512897A (es) |
KR (1) | KR100371669B1 (es) |
CN (1) | CN1183706C (es) |
AU (1) | AU715522B2 (es) |
BR (1) | BR9610944A (es) |
CA (1) | CA2233069A1 (es) |
MX (1) | MX9802332A (es) |
NO (1) | NO981245L (es) |
SE (1) | SE506739C2 (es) |
WO (1) | WO1997012457A2 (es) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999009687A1 (en) * | 1997-08-13 | 1999-02-25 | Alcatel Usa Sourcing, L.P. | System and apparatus for timing signal generation and control |
TW457389B (en) * | 1998-03-23 | 2001-10-01 | Toshiba Corp | Liquid crystal display element |
US6526370B1 (en) * | 1999-02-04 | 2003-02-25 | Advanced Micro Devices, Inc. | Mechanism for accumulating data to determine average values of performance parameters |
US6895525B1 (en) * | 1999-08-20 | 2005-05-17 | International Business Machines Corporation | Method and system for detecting phase-locked loop (PLL) clock synthesis faults |
US6633989B1 (en) * | 1999-11-30 | 2003-10-14 | Lsi Logic Corporation | Method and mechanism for synchronizing a slave's timer to a master's timer |
US6721896B1 (en) * | 2000-03-31 | 2004-04-13 | Alcatel | System and method for converting a selected signal into a timing signal and inserting the phase of the timing signal into a framed signal |
US7254470B2 (en) * | 2002-06-17 | 2007-08-07 | Delphi Technologies, Inc. | Fault tolerant torque sensor signal processing |
ATE329422T1 (de) * | 2002-12-12 | 2006-06-15 | Cit Alcatel | Defektsignalisierung für hardware unterstützte ersatzschaltung in einem optischen querverbindungssystem |
US7075365B1 (en) | 2004-04-22 | 2006-07-11 | Altera Corporation | Configurable clock network for programmable logic device |
JP5267218B2 (ja) * | 2009-03-05 | 2013-08-21 | 富士通株式会社 | クロック供給方法及び情報処理装置 |
EP2228926B1 (en) * | 2009-03-12 | 2017-08-30 | Alcatel Lucent | Method for synchronizing clocks by seperated transmissions of first and second data via at least one timing distribution protocol, and associated system and module |
CN101695188B (zh) * | 2009-10-15 | 2012-01-04 | 上海华为技术有限公司 | 校正本地时间的方法以及时钟服务器 |
AT509700B1 (de) * | 2010-04-07 | 2019-05-15 | Tttech Computertechnik Ag | Verfahren und apparat zur fehlertoleranten zeitgesteuerten echtzeitkommunikation |
JP5742461B2 (ja) * | 2011-05-20 | 2015-07-01 | 日本電気株式会社 | 信号伝送装置 |
US9094906B2 (en) * | 2011-11-11 | 2015-07-28 | Telefonaktiebolaget Lm Ericsson (Publ) | Multi-stage timing and frequency synchronization |
CN102700718B (zh) * | 2012-06-29 | 2014-04-16 | 中国航空工业集团公司第六三一研究所 | 通用飞机航空电子系统告警信息处理方法 |
US9336074B2 (en) * | 2013-07-26 | 2016-05-10 | Honeywell International Inc. | Apparatus and method for detecting a fault with a clock source |
CN104515945B (zh) * | 2013-09-27 | 2018-04-17 | 伊姆西公司 | 隐藏故障检测电路及利用隐藏故障检测电路检测隐藏故障的方法 |
KR102161821B1 (ko) * | 2014-08-26 | 2020-10-06 | 삼성전자주식회사 | 클록 모니터 및 이를 포함하는 시스템 온 칩 |
CN107729614A (zh) * | 2017-09-18 | 2018-02-23 | 北京空间飞行器总体设计部 | 一种可扩展的通用功能级异步电路 |
CN108259108B (zh) * | 2018-01-26 | 2019-09-27 | 郑州云海信息技术有限公司 | 一种多节点服务器冗余同源时钟系统及时钟选择方法 |
CN110442187B (zh) * | 2019-08-08 | 2021-05-28 | 南京芯驰半导体科技有限公司 | 针对模块的时钟限制系统及其方法 |
CN111307837B (zh) * | 2020-03-20 | 2022-07-01 | 中国核动力研究设计院 | 一种夹持于流道的放射物含量测量装置及模型建立方法 |
CN111294022B (zh) * | 2020-03-23 | 2022-10-28 | 中国科学技术大学 | 序列信号发生器 |
Family Cites Families (31)
Publication number | Priority date | Publication date | Assignee | Title |
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US4105900A (en) | 1977-02-16 | 1978-08-08 | The Boeing Company | Signal selection apparatus for redundant signal sources |
US4185245A (en) | 1978-05-15 | 1980-01-22 | International Telephone And Telegraph Corporation | Fault-tolerant clock signal distribution arrangement |
US4239982A (en) | 1978-06-14 | 1980-12-16 | The Charles Stark Draper Laboratory, Inc. | Fault-tolerant clock system |
FR2513471A1 (fr) | 1981-09-18 | 1983-03-25 | Cit Alcatel | Dispositif de distribution de signaux pour autocommutateur temporel |
US4598257A (en) * | 1983-05-31 | 1986-07-01 | Siemens Corporate Research & Support, Inc. | Clock pulse signal generator system |
JPS60225982A (ja) | 1984-04-24 | 1985-11-11 | Japanese National Railways<Jnr> | 3重系におけるクロツクパルス同期装置 |
FR2577087B1 (fr) * | 1985-02-07 | 1987-03-06 | Thomson Csf Mat Tel | Dispositif de distribution d'horloge tripliquee, chaque signal d'horloge comportant un signal de synchronisation |
FR2577088B1 (fr) * | 1985-02-07 | 1987-03-06 | Thomson Csf Mat Tel | Repeteur pour distribution d'horloge tripliquee |
US4672299A (en) * | 1986-05-23 | 1987-06-09 | American Telephone And Telegraph Co. | Clock control circuit for phase control |
US4788670A (en) * | 1987-08-18 | 1988-11-29 | Siemens Aktiengesellschaft | Clock voltage supply |
JPH0797328B2 (ja) | 1988-10-25 | 1995-10-18 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | フオールト・トレラント同期システム |
US5008636A (en) | 1988-10-28 | 1991-04-16 | Apollo Computer, Inc. | Apparatus for low skew system clock distribution and generation of 2X frequency clocks |
AU625293B2 (en) * | 1988-12-09 | 1992-07-09 | Tandem Computers Incorporated | Synchronization of fault-tolerant computer system having multiple processors |
EP0394725B1 (de) | 1989-04-28 | 1996-02-14 | Siemens Aktiengesellschaft | Taktverteilereinrichtung |
SE466475B (sv) * | 1990-07-10 | 1992-02-17 | Ericsson Telefon Ab L M | Saett och anordning foer oevervakning och testning vid en flerplansenhet i en digital tidsvaeljare |
US5381542A (en) * | 1991-07-29 | 1995-01-10 | Unisys Corporation | System for switching between a plurality of clock sources upon detection of phase alignment thereof and disabling all other clock sources |
US5276690A (en) * | 1992-01-30 | 1994-01-04 | Intel Corporation | Apparatus utilizing dual compare logic for self checking of functional redundancy check (FRC) logic |
JP3375658B2 (ja) * | 1992-03-19 | 2003-02-10 | 株式会社日立製作所 | 並列計算機およびそのためのネットワーク |
US5377325A (en) * | 1992-04-21 | 1994-12-27 | Acer Incorporated | Bidirectional wait control between host module and slave module |
US5537655A (en) * | 1992-09-28 | 1996-07-16 | The Boeing Company | Synchronized fault tolerant reset |
US5524237A (en) * | 1992-12-08 | 1996-06-04 | Zenith Electronics Corporation | Controlling data transfer between two microprocessors by receiving input signals to cease its data output and detect incoming data for reception and outputting data thereafter |
US5581794A (en) * | 1992-12-18 | 1996-12-03 | Amdahl Corporation | Apparatus for generating a channel time-out signal after 16.38 milliseconds |
SE501156C2 (sv) | 1993-04-21 | 1994-11-28 | Ellemtel Utvecklings Ab | Referenssignal sammansatt av klocksignal och synkroniseringssignal, anordning och förfarande för synkronisering m.h.a. referenssignal |
EP0974912B1 (en) * | 1993-12-01 | 2008-11-05 | Marathon Technologies Corporation | Fault resilient/fault tolerant computing |
US5642069A (en) * | 1994-04-26 | 1997-06-24 | Unisys Corporation | Clock signal loss detection and recovery apparatus in multiple clock signal system |
KR970000265B1 (ko) * | 1994-09-26 | 1997-01-08 | 엘지반도체 주식회사 | 데이타전송율 자동검출회로 |
US5537583A (en) * | 1994-10-11 | 1996-07-16 | The Boeing Company | Method and apparatus for a fault tolerant clock with dynamic reconfiguration |
US5852728A (en) * | 1995-01-12 | 1998-12-22 | Hitachi, Ltd. | Uninterruptible clock supply apparatus for fault tolerant computer system |
US5758132A (en) * | 1995-03-29 | 1998-05-26 | Telefonaktiebolaget Lm Ericsson | Clock control system and method using circuitry operating at lower clock frequency for selecting and synchronizing the switching of higher frequency clock signals |
KR0174596B1 (ko) * | 1995-05-10 | 1999-04-01 | 김광호 | 교환시스템의 망동기제어를 위한 클럭수신회로 |
US5898895A (en) * | 1996-10-10 | 1999-04-27 | Unisys Corporation | System and method for controlling data transmission rates between circuits in different clock domains via selectable acknowledge signal timing |
-
1995
- 1995-09-29 SE SE9503371A patent/SE506739C2/sv not_active IP Right Cessation
-
1996
- 1996-09-27 AU AU71515/96A patent/AU715522B2/en not_active Ceased
- 1996-09-27 KR KR10-1998-0702366A patent/KR100371669B1/ko not_active IP Right Cessation
- 1996-09-27 CA CA002233069A patent/CA2233069A1/en not_active Abandoned
- 1996-09-27 BR BR9610944A patent/BR9610944A/pt not_active IP Right Cessation
- 1996-09-27 WO PCT/SE1996/001211 patent/WO1997012457A2/en active IP Right Grant
- 1996-09-27 JP JP9513359A patent/JPH11512897A/ja not_active Ceased
- 1996-09-27 EP EP96932911A patent/EP0852860A1/en not_active Withdrawn
- 1996-09-27 CN CNB961984252A patent/CN1183706C/zh not_active Expired - Fee Related
-
1998
- 1998-03-19 NO NO981245A patent/NO981245L/no unknown
- 1998-03-25 MX MX9802332A patent/MX9802332A/es not_active IP Right Cessation
- 1998-03-27 US US09/049,327 patent/US6195758B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
WO1997012457A3 (en) | 1997-04-24 |
WO1997012457A2 (en) | 1997-04-03 |
AU7151596A (en) | 1997-04-17 |
CN1183706C (zh) | 2005-01-05 |
NO981245D0 (no) | 1998-03-19 |
JPH11512897A (ja) | 1999-11-02 |
EP0852860A1 (en) | 1998-07-15 |
SE9503371D0 (sv) | 1995-09-29 |
SE506739C2 (sv) | 1998-02-09 |
AU715522B2 (en) | 2000-02-03 |
SE9503371L (sv) | 1997-03-30 |
NO981245L (no) | 1998-05-26 |
BR9610944A (pt) | 1999-01-12 |
KR19990063894A (ko) | 1999-07-26 |
CN1202997A (zh) | 1998-12-23 |
US6195758B1 (en) | 2001-02-27 |
CA2233069A1 (en) | 1997-04-03 |
KR100371669B1 (ko) | 2003-04-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG | Grant or registration | ||
MM | Annulment or lapse due to non-payment of fees |