MX2020000952A - Motor matematico acelerado. - Google Patents

Motor matematico acelerado.

Info

Publication number
MX2020000952A
MX2020000952A MX2020000952A MX2020000952A MX2020000952A MX 2020000952 A MX2020000952 A MX 2020000952A MX 2020000952 A MX2020000952 A MX 2020000952A MX 2020000952 A MX2020000952 A MX 2020000952A MX 2020000952 A MX2020000952 A MX 2020000952A
Authority
MX
Mexico
Prior art keywords
accelerated
mathematical engine
engine
mathematical
image
Prior art date
Application number
MX2020000952A
Other languages
English (en)
Inventor
Peter Joseph Bannon
Kevin Altair Hurd
Emil Talpes
Original Assignee
Tesla Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tesla Inc filed Critical Tesla Inc
Publication of MX2020000952A publication Critical patent/MX2020000952A/es

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/045—Combinations of networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Physics (AREA)
  • Data Mining & Analysis (AREA)
  • Biophysics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Software Systems (AREA)
  • General Health & Medical Sciences (AREA)
  • Computational Linguistics (AREA)
  • Artificial Intelligence (AREA)
  • Molecular Biology (AREA)
  • Evolutionary Computation (AREA)
  • Computer Hardware Design (AREA)
  • Neurology (AREA)
  • Algebra (AREA)
  • Databases & Information Systems (AREA)
  • Image Processing (AREA)
  • Complex Calculations (AREA)
  • Image Analysis (AREA)

Abstract

Varias modalidades de la divulgación se relacionan con un motor matemático acelerado; en ciertas modalidades, el motor matemático acelerado es aplicado a procesamiento de imágenes para que se acelere la convolución de una imagen al utilizar un procesador de matriz bidimensional que comprende sub-circuitos que incluyen una ALU, un registro de salida y registro de sombra; esta arquitectura soporta una arquitectura cronometrada bidimensional en la que se multiplican datos y pesos de imágenes de una manera sincronizada para permitir que un gran número de operaciones matemáticas sean llevadas a cobo de forma paralela.
MX2020000952A 2017-07-24 2018-07-19 Motor matematico acelerado. MX2020000952A (es)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201762536399P 2017-07-24 2017-07-24
US15/710,433 US10671349B2 (en) 2017-07-24 2017-09-20 Accelerated mathematical engine
PCT/US2018/042959 WO2019023046A1 (en) 2017-07-24 2018-07-19 ACCELERATED MATHEMATICAL MOTOR

Publications (1)

Publication Number Publication Date
MX2020000952A true MX2020000952A (es) 2020-07-22

Family

ID=65018989

Family Applications (2)

Application Number Title Priority Date Filing Date
MX2020000952A MX2020000952A (es) 2017-07-24 2018-07-19 Motor matematico acelerado.
MX2023010407A MX2023010407A (es) 2017-07-24 2020-01-24 Motor matematico acelerado.

Family Applications After (1)

Application Number Title Priority Date Filing Date
MX2023010407A MX2023010407A (es) 2017-07-24 2020-01-24 Motor matematico acelerado.

Country Status (8)

Country Link
US (4) US10671349B2 (es)
EP (2) EP4258182A3 (es)
JP (3) JP7009609B2 (es)
KR (4) KR102353241B1 (es)
CN (2) CN117171480A (es)
CA (1) CA3070972C (es)
MX (2) MX2020000952A (es)
WO (1) WO2019023046A1 (es)

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