CN111095241A - 加速数学引擎 - Google Patents

加速数学引擎 Download PDF

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CN111095241A
CN111095241A CN201880058445.1A CN201880058445A CN111095241A CN 111095241 A CN111095241 A CN 111095241A CN 201880058445 A CN201880058445 A CN 201880058445A CN 111095241 A CN111095241 A CN 111095241A
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P·J·班农
K·A·胡德
E·塔尔佩斯
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Abstract

本公开的各种实施例涉及一种加速数学引擎。在某些实施例中，加速数学引擎被应用于图像处理，使得图像的卷积通过使用包括子电路的二维矩阵处理器而被加速，子电路包括ALU、输出寄存器和影子寄存器。该架构支持时钟二维架构，其中图像数据和权重以同步方式相乘，以允许大量数学运算被并行执行。

Description

加速数学引擎
相关申请的交叉引用
本申请要求于2017年7月24日提交的标题为“Accelerated MathematicalEngine”、并且列出Peter Joseph Bannon、Kevin Altair Hurd和Emil Talpes作为发明人的美国临时专利申请第62/536,399号(20150-2154P(P0822-1PUS))的优先权权益。前述专利文件通过引用全部并入本文。
本申请还要求于2017年9月20日提交的标题为“Accelerated MathematicalEngine”、并且列出Peter Joseph Bannon、Kevin Altair Hurd和Emil Talpes作为发明人的共同拥有的美国专利申请第15/710,433号(20150-2154(N0822-1NUS))的优先权权益。前述专利文件中的每一个通过引用全部并入本文。
背景技术
A.技术领域
本公开涉及一种用于对大量数据进行操作的加速数学引擎，更具体地涉及一种用于基于矩阵乘法操作来执行复杂卷积操作的加速数学引擎。
B.相关领域描述
本领域技术人员将认识到对用于实施对时间敏感且复杂的数学操作的通用处理器和系统的速度和性能的不断增长的需求。由于这些通用系统用于处理大量数据并且执行复杂的数学操作，因此计算资源和计算速率受到执行这些计算的现有通用硬件设计能力的限制。例如，在某些情况下，执行矩阵操作的通用计算设备和处理器可能无法及时执行这些运算。执行数字信号处理操作的许多传统乘法器依赖于一系列软件和硬件矩阵操作操纵步骤(地址生成、换位、逐位加法和移位等)，并且可能表示对时间敏感的系统内的瓶颈。通常，由于增加了从各个位置存储和获取中间结果以完成操作的步骤，这些操纵步骤需要使用处理器的算术函数来生成中间结果，但是却浪费了计算时间。
图1示出了传统乘法器系统的示例。乘法器系统100是包括计算单元102、寄存器104、高速缓存106和存储器108的标量机。在操作中，计算单元102使用寄存器104和高速缓存106来检索存储在存储器108中的数据。通常，计算单元102是微处理器，诸如能够执行各种计算进程(包括对输入矩阵进行矩阵乘法以获得结果矩阵)的CPU或GPU例如，通过将乘法转换为加法并且将结果输出到某个内部寄存器中。
例如，表示图像的输出像素的点积通常通过对来自两个矩阵的各个矩阵元素进行点乘以获得部分结果、然后将部分结果相加以获得最终点积而生成。通常，通过将点乘分解成一系列的单个子操作，来对单个数据元素执行单个矩阵元素的乘法，即，标量乘法。因此，部分积必须被存储，并且从寄存器104、高速缓存106和存储器108中的一个或多个被获取，以完成单个算术运算。
对计算有要求的应用(诸如卷积)通常需要被嵌入到计算单元102中并且用于将卷积操作转换为交替的矩阵乘法操作的软件功能。这通过将数据重新排列并重新格式化为随后能够进行原始矩阵相乘的两个矩阵而完成。然而，在标量机100中不存在高效地共享或重用数据的机制，使得执行每个标量操作所需的数据必须被多次重新存储并从寄存器中多次重新获取。随着要进行卷积操作的图像数据量的增加，这些操作的复杂性和管理开销将变得明显更大。
不能重用标量机100中的许多数据以及所增加且效率低下的从寄存器104、高速缓存106和存储器108存储和获取中间结果以完成算术运算的步骤只是现有系统(诸如乘法器系统100)的一些缺点。
因此，需要可以快速且高效地执行矩阵数学操作的高计算吞吐量系统和方法。
附图说明
将参照本发明的实施例，本发明的实施例的示例可以在附图中图示。这些附图旨在是说明性的，而非限制性的。尽管通常在这些实施例的上下文中描述了本发明，但是应该理解，并不旨在将本发明的范围限制为这些特定实施例。附图中的项目可能未按比例绘制。
图(“FIG.”)1示出了传统乘法器系统的示例。
图2图示了根据本公开的各种实施例的用于执行算术运算的示例性矩阵处理器架构。
图3图示了图2所示的矩阵处理器架构的示例性配置的细节。
图4图示了图3所示的逻辑电路的示例性乘加电路的实施方式。
图5图示了根据本公开的各种实施例的示例性卷积操作。
图6至图8图示了根据本公开的各种实施例的示例性卷积操作的细节。
图9图示了根据本公开的各种实施例的示例性去卷积操作。
图10图示了根据本公开的各种实施例的用于执行算术运算以使卷积神经网络更快的过程。
具体实施方式
在以下描述中，出于解释的目的，陈述了特定细节以便提供对本发明的理解。然而，对于本领域技术人员显而易见的是，可以在没有这些细节的情况下实践本发明。此外，本领域技术人员将认识到，下面描述的本发明的实施例可以以多种方式来实施，诸如，过程、装置、系统、设备者或有形计算机可读介质上的方法。
图中所示的组件或模块是本发明的示例性实施例的说明，并且意在避免使本发明晦涩难懂。还应该理解，在整个讨论中，组件可以被描述为单独的功能单元，其可以包括子单元，但是本领域技术人员将认识到，各种组件或其一部分可以被划分为单独的组件或者可以集成在一起，包括集成在单个系统或单个组件内。应该注意的是，本文讨论的功能或操作可以被实施为组件。组件可以以软件、硬件或其组合来实施。许多组件是通过将许多子组件互连而形成的。可以选择在操作中与本文所示的逻辑上不同的子组件，其中这些逻辑上不同的子组件可以与其他子组件组合在一起，该其他子组件在聚合组件级别上提供与本文描述的功能性类似或相同的功能性(例如，有源高信号可以是有源低的，AND门被替换为具有反向输入的NOR门等)。
此外，附图内的组件或系统之间的连接不旨在限于直接连接。相反，中间组件可以被修改，重新格式化或者以其他方式改变这些组件之间的数据。而且，可以使用附加或更少的连接。还应该注意的是，术语“耦合”、“连接”或“通信耦合”应该理解为包括直接连接、通过一个或多个中间设备的间接连接、以及无线连接。
在说明书中对“一个实施例(one embodiment)”、“优选实施例”、“一个实施例(anembodiment)”或“实施例”的引用是指结合该实施例描述的特定特征、结构、特性或功能被包括在本发明的至少一个实施例中，并且可以在一个以上的实施例中。而且，说明书中的各个地方的上述短语的出现不一定全部指代相同的一个或多个实施例。
在说明书中的各个地方使用某些术语是为了说明的目的，而不应解释为进行限制。服务、功能或资源不限于单个服务、功能或资源；这些术语的使用可能是指相关服务、功能或资源的分组，它们可以进行分布或聚合。
术语“包括(include)”、“包括(including)”、“包括(comprise)”和“包括(comprising)”应被理解为开放式术语，并且随附的任何列表都是示例，并不意味着限于所列出的项目，并且可以包括项目的子集合或超集合以及附加项目。本文使用的任何标题仅用于组织目的，并且不应该用于限制说明书或任何权利要求的范围。该专利文件中提到的每个文件均通过引用全部并入本文。
此外，本领域技术人员应该认识到：(1)可能可选地执行某些步骤；(2)步骤可能不限于本文列出的特定顺序；(3)某些步骤可能以不同的顺序执行；以及(4)某些步骤可能同时进行。
尽管本文的实施例主要是在卷积的上下文中讨论的，但是本领域技术人员将了解，去卷积和其他矩阵操作也可以被构造为矩阵-矩阵类型的乘法操作，因此，本发明的原理同样适用于去卷积。此外，根据本公开的各种实施例，可以实施其他类型的数学操作。
图2图示了根据本公开的各种实施例的用于执行算术运算的示例性矩阵处理器架构。系统200包括逻辑电路232 234、高速缓存/缓冲器224、数据格式器210、权重格式器212、数据输入矩阵206、权重输入矩阵208、矩阵处理器240、输出阵列226、后处理单元228以及控制逻辑250。矩阵处理器240包括多个子电路242，其包含算术逻辑单元(ALU)、寄存器以及在一些实施例中的编码器(诸如，booth编码器)。逻辑电路232可以是表示N个输入操作符和数据寄存器的电路。逻辑电路234可以是将M个权重操作数输入到矩阵处理器240中的电路系统。逻辑电路232可以是将图像数据操作数输入到矩阵处理器240中的电路系统。权重输入矩阵208和数据输入矩阵206可以被存储在包括SRAM设备的各种类型的存储器中。本领域技术人员将认识到，可以将各种类型的操作数输入到矩阵处理器240中。
在根据某些实施例的操作中，系统200通过减少系统内的冗余操作并实施特定于硬件的逻辑以跨大量数据和权重执行某些数学操作来加速卷积操作。该加速是方法(和对应的硬件组件)的直接结果，该方法检索图像数据和权重并将其输入到矩阵处理器240，以及大规模地对矩阵处理器240内的数学操作进行定时。
在实施例中，格式器210 212在图2的示例中被实施为行内格式器。在某些实施例中，格式器210 212是离散的组件，而在其他实施例中，格式器210 212被集成在一起和/或与一个或多个其他组件集成在一起。每个格式器都以硬件实施，并将矩阵转换为要在矩阵处理器240内进行操作的操作数上的向量。在其他实施例中，格式器210 212以软件实施，尽管这通常会产生速度损失。数据格式器210将包括数据输入矩阵206的二维或三维(例如，3x3x3立方体)数据转换成可以由行或列表示的单个向量或字符串，从而线性化或向量化数据输入矩阵206。具体而言，格式器210接收数据输入矩阵206并准备要由矩阵处理器240处理的输入数据。在实施例中，这是通过根据矩阵处理器240的硬件要求将数据输入矩阵206的参数映射为合适的格式来完成，使得矩阵处理器240可以在生成输出像素时高效地执行矩阵乘法，作为卷积计算的一部分。
作为示例，假设矩阵处理器240包括96行和96列，则映射为96x96格式的数据将使矩阵处理器240发挥其全部计算能力，从而提供优选的效率。在这种情况下，格式器210应该产生96列宽的输出。同样地，格式器212应该基于权重输入矩阵208来产生96行宽的输出。
在实施例中，格式器210使用多个复用器或开关来获取数据输入矩阵206中的一些或全部，并从中选择不同的元素，以便产生随后根据矩阵处理器240的列进行排列的数据。在实施例中，该选择确保来自数据输入矩阵206的适当数据被传递到在所定义的时钟周期内的每个列。在实施例中，如果权重是静态的，则它们可以被离线预先格式化、存储在存储器中、仅被获取一次、并且以修改的向量化格式直接馈送到矩阵处理器240中而无需使用格式器212。在其他实施例中，权重可以根据各种格式化和获取操作而被动态地调整并且被馈送到矩阵处理器240中。在实施例中，矩阵处理器240允许变化大小的列和行输入。即，矩阵处理器240被设计为计算任意大小的N×M计算。
在其他实施例中，如果矩阵处理器240的列数受到限制(例如，限制为N列)，使得数据输入矩阵206中的列数(例如，X)大于矩阵处理器240的列数(即，X>N)，那么控制逻辑250可以将数据输入矩阵206分为多个子矩阵，其中每个子矩阵由矩阵处理器240计算。在这种情况下，每个矩阵处理器240可以在不同的线程中运行。例如，如果数据输入矩阵206由192x96个数据点组成，并且矩阵处理器具有96列和96行(即，可以在一个时钟周期中进行96x96次计算)，则控制逻辑250可以将数据输入矩阵206分为两个子矩阵(诸如，数据输入矩阵206的左半部分和数据输入矩阵206的右半部分)。每个子矩阵将由96x96个数据点组成。每个单独线程的矩阵处理器240可以计算用于发送给它的子矩阵的输出通道，其中结果被放入最终输出阵列260中，该最终输出阵列260必须足够大以容纳来自所有通道的值(即，192个值)。更一般地，数据输入矩阵206可以被分成任何数目的子矩阵，并且被发送到不同的矩阵处理器240，每个矩阵处理器在单独的线程中运行。与输出阵列226一样，数据输入矩阵206、数据格式器210、高速缓存/缓冲器224、逻辑电路232和后处理单元228必须类似地能够容纳更大的数据。
在替代实施例中，可以通过使控制逻辑250沿着内积对计算进行划分来在多个矩阵处理器240之间计算CNN。分别在不同的矩阵处理器240中计算内积的片段，然后将输入的积相加在一起以计算输出向量，然后将输出向量存储在输出阵列260中。
与由CPU或GPU执行以通过将数据重新布置为适合于快速矩阵乘法的替代格式来将卷积操作转换为矩阵乘法的格式化功能的通用软件实施方式不同，本发明的各种硬件实施方式动态地重新格式化数据并使之可用于执行，例如，实际上每个周期96个数据，从而允许并行处理大量矩阵元素，因此高效地将数据映射到矩阵操作。在实施例中，针对2N个获取的输入数据，可以在单个时钟周期中获得2N2个计算数据。通过有效减少典型处理器架构中使用的读取或获取操作的数目以及在跨多个数据输入执行大量数学操作时提供并行、高效且同步的过程，该架构显着提高了处理速度。
在实施例中，为了增加可以具有任意数目的列和行的矩阵处理器240的效率，格式器212 214可以将不同形状的输入矩阵数据重新格式化为适合于矩阵处理器240的列和行。在实施例中，动态地执行格式化以适应具有不同输入大小的矩阵的处理。在实施例中，将包括输入通道的重新格式化的矩阵馈送到高速缓存/缓冲器224中。
高速缓存/缓冲器224可以仅从数据输入矩阵206获取数据1/k次，因为可以重用各种数据，其中k是卷积内核宽度。例如，针对任何给定的周期，一旦获取一行，某些列将有权访问该行中的所有数据。在实施例中，高速缓存/缓冲器224可以是本地缓冲器，其存储可以由卷积重用的数据的本地副本，而不必重新访问数据并从SRAM读取数据。
一旦矩阵处理器240完成了计算，就可以将结果集合从例如矩阵处理器240的底行中的累加器移位到例如输出触发器(未示出)，该输出触发器有效地形成接收点积的移位寄存器。在实施例中，可以通过状态机(未示出)来将结果从对应于输出通道的行中拉出或移位到输出阵列226中，例如，每个时钟周期一个输出阵列。状态机可以在输出通道上执行附加操作，例如，在将数据发送给SRAM和/或后处理单元228之前。将在下面更详细地描述矩阵处理器240的内部操作。
在实施例中，矩阵处理器240包括影子电阻器，该影子电阻器通过存储通过矩阵处理器240传递到输出阵列226的结果的副本来实现并行处理。在实施例中，将操作结果从输出寄存器移动到影子寄存器涉及将下一组值加载到ALU中。
一旦累加完成，在将先前卷积的所有数据输出到输出阵列226之前，可以开始卷积并且可以重新开始累加。因此，在每个时钟周期中，矩阵处理器240中的数据可以向下移动一行，使得针对每个周期，最后一行可以输出到输出阵列226。实际上，这种操作模式确保了可以在每个连续周期中进行新的计算而不会产生任何中断，并且独立于附加的处理操作，诸如，将数据存储在SRAM中等。
后处理单元228可以包括多个设备(未示出)或与多个设备(未示出)交互，诸如硬件加速的池化单元、DRAM等，该DRAM可以是从存储器中检索数据并且将数据(例如，权重和结果)存储在SRAM中的直接存储器访问(“DMA”)的一部分。设备可以由控制逻辑250部分或全部控制，该控制逻辑250也可以管理格式器210212和系统200内的其他组件。
在图2中未示出的是执行管理功能的辅助设备，诸如定序器，该定序器生成用于读取数据的地址、写入结果并追踪系统200在卷积中的位置，以便计算从何处获得数据以及如何执行将在卷积的后续步骤中使用的数据。
在某些实施例中，权重输入矩阵208被物理地划分并且从矩阵处理器240的两个不同侧驱动权重，使得二维阵列被分为两个区域(例如，左手侧和右手侧)，每个区域接收权重输入矩阵208中的数据的一部分。这种实施方式通过利用权重已知的事实来减少数据延迟。在实施例中，为了减少峰值功率消耗，可以选择操作的定时，使得权重和数据的乘法分布在一定数目的周期内。操作的这种有效定时导致能量消耗步骤的减少，包括减少由矩阵处理器执行的读取操作的数目，并提高矩阵内(例如，子电路之间)的数据移动的效率。
在实施例中，可以采用被配置为标识冗余数据的状态机(未示出)。标识出的冗余数据可以跨列重用，使得无需重新获取数据。状态机可以被配置为例如基于与图像大小、滤波器大小、步幅、通道数和类似参数相关的输入来确定如何以及在何处移位将要执行的数据。
在实施例中，在矩阵处理器240的乘法架构中的多个元件之间共享booth编码器。booth编码器可以是本领域中已知的任何booth编码器，并且可以用于将两个数字相乘并对两个数字中的一个数字编码，例如，从8位值到12位或者使乘法操作在乘法器逻辑上更容易并因此更快的任何其他值。在实施例中，可以在整个行上并行应用booth编码器，以便在所有列上共享相同的编码的替代权重值。通过跨所有列加载操作数，可以跨整个行在单个时钟周期中执行乘法。因此，针对N个计算元素，利用重新编码以共享相同数据(例如，权重)的成本对于每一列(或行)仅支付一次。相比之下，在现有的计算架构中，每个单个标量对于每个单个乘法操作都将需要booth编码器。
图3图示了图2所示的矩阵处理器架构的示例性配置的细节。在实施例中，矩阵处理器300可以在每个轴线上容纳预定的向量长度。如图3所描绘的，矩阵处理器300可以包括以矩阵格式布置的6x 6图块302的阵列。每个图块302可以包括矩阵320，该矩阵320又包括子电路电路350。如下面参照图4详细讨论的，每个子电路电路350可以是能够执行算术运算的单元。在实施例中，子电路电路350同时执行乘法、累加和移位操作。
在实施例中，通过利用矩阵处理器300的多个行和列来并行化算术运算以生成NxN个图块输出。例如，给定的行大小为96和对应的列大小为96有助于2*9216次数学计算的输出。在其他实施例中，行和列的数目可以不同。即，可以存在N行和M列，并且可以生成N×M个图块输出。例如，针对96的行大小和192的对应列大小，在单个时钟周期中生成2*18,432次计算的输出。
图4图示了图3所示的子电路的示例性乘加(multiply-and-add)电路实施方式。如图4所描绘的，乘加电路400包括乘法器430、加法器432、逻辑434 436 438、累加器424、影子寄存器428和输出寄存器440。在实施例中，累加器424可以被实施为累加寄存器。
在实施例中，累加器424可以包括由寄存器组成的一组ALU，以及可以被配置为接收ALU的输出的影子寄存器428。
在操作中，乘法器430接收权重402和数据404并将其相乘以从中生成乘积。可以将每个乘积提供给加法器432，加法器432响应于从乘法器430接收到乘积而将该乘积与累加器424的当前值相加。
在实施例中，累加器424生成例如存储在输出寄存器440中的累加值。该累加值是卷积的结果，并且如参照图2所提及的，可以对应于两个格式化矩阵的点积。
在实施例中，可以将输出寄存器440中的结果的副本提供给影子寄存器428，其可以输出结果450，使得可以再次访问累加器424以开始新的计算。在实施例中，图4中的乘加电路400可以同时(即，在单个周期内)执行乘法、加法操作和移位操作，从而使每个周期发生的操作总数加倍。
在实施例中，例如，当乘法器430执行乘法操作时，ClearAcc信号408清除累加器424的内容，使得累加操作可以重新开始。在实施例中，响应于确定数据404有效而激活ResultEnable信号412。要理解的是，累加器424可以累加和保存数据，累加和清除数据，或仅清除数据。
在实施例中，结果在单个时钟周期中从输出寄存器440移动到影子寄存器428，即，无需中间执行和保存操作。
图5图示了根据本公开的各种实施例的示例性卷积操作。卷积500包括输入图像502的输入通道IC、权重532、点积514、输出通道OC和累加器540。
在实施例中，卷积操作500将单独的滤波器(即，权重)532应用于输入图像502，例如，以检测输入图像502内的小特征。通过以不同顺序分析不同特征的序列，然后可以在输入图像502中标识宏特征。在其他实施例中，输入502是非图像数据。例如，输入502可以是非图像传感器数据，诸如，超声、雷达、LIDAR或其他传感器数据。输入502也可以是通用数学计算或本领域技术人员已知的任何其他类型的数据。
卷积500可以为每个输入通道IC使用不同的权重集合532，因为每个输入通道IC可以包含不同的信息集合，并且每个权重矩阵532可以被设计为帮助标识不同的特征。在实施例中，卷积500将矩形输入矩阵504与矩形权重矩阵532相乘以获得部分点积。然后可以通过加法器546对部分点积求和，以生成表示输出图像中的输出像素514的累积点积514(即，整数)。
在实施例中，输出通道OC中的每个像素是由乘法器542和加法器544生成的。在实施例中，部分点积的值对应于权重矩阵532整体上对输入图像502的区域504的应用。换言之，乘法器542将每个权重532与区域504进行点乘以产生部分点积，然后部分点积在累加器540中累积以生成表示卷积的累积输出。
可以使用一个或多个输入通道IC，例如，每种颜色(例如，RGB)一个输入通道。例如，每个卷积可以使用表示三种不同矩阵的权重532，每种颜色一种权重。可以使用表示输入数据502中的不同特征的不同的滤波器或权重532来生成每个输出通道OC 512。输出通道的数目可以取决于特征的数目。卷积数等于输出通道OC的数目乘以输入通道IC的数目，并且针对每个输入通道IC，每个卷积可以具有N个卷积。本领域技术人员将认识到，输入通道的数目和类型可以变化，并且可以包括颜色和/或透明输入。
如图5所描绘的，输入矩阵504是Kx x Ky(即，3x3)矩阵，其可以与跨3个输入通道(即，3x3x IC)的3x3权重矩阵532组合，使得深度匹配并产生输出平面中的单个元素，即点积514。输出通道512中的每个点积514是点乘的结果。
图6至图8图示了根据本公开的各种实施例的示例性卷积操作的细节。卷积600包括输入数据矩阵602、权重数据矩阵604、阵列606以及点积630。在实施例中，阵列606是如图2和图3所示的矩阵处理器架构。
图6中的输入数据矩阵602包括列610，在实施例中，列610可以通过线性化输入矩阵(诸如，图5所示的矩形输入矩阵504)而获得，以获得输入矩阵的向量化形式。同样地，权重数据矩阵604包括行620，其可以是权重矩阵(诸如，图5中的矩形权重矩阵532)的向量化形式。作为示例，可以将3x3输入矩阵和3个输入通道重新格式化为包括3x3x3＝27个元素的向量，可以从该向量中产生27个元素的列610以用于输入数据矩阵602。相反，用于相同的3个输入通道的3x3权重矩阵可以用于生成27个元素的行620以用于权重数据矩阵604。本领域技术人员将认识到，输入矩阵的大小和输入通道的数目可能会因不同的应用而异。
在实施例中，例如，通过参照图2讨论的格式器来将在图5中绘制为矩形的输入通道和输入权重重新格式化为向量格式(例如，具有96个元素的向量)，该向量格式被提供给矩阵乘法器/处理器(表示为图2的元素240)，使得可以并行执行96x96个元素的点积操作。详细地，针对每个输入通道在图5中示出为矩形的输入数据504和输入权重532被重新格式化为向量格式。
在实施例中，在图6中被图示为输入数据602和输入权重604(例如，每个具有96个元素)的所得向量格式被提供给并行执行96x96个元素点积操作的矩阵处理器或矩阵乘法器240。在实施例中，在输出通道的计算中，使用相同的输入数据集合但是使用不同的权重集合(即，滤波器)来产生相同的输出像素，使得通过一次读取输入数据，可以一次生成许多输出通道。如上所述，要理解的是，输入和输出通道的数目可以任意选择。
要进一步理解的是，输入数据矩阵602、权重数据矩阵604和阵列606可以具有与图6所描绘的列和行不同的数目。具体地，输入数据矩阵602和权重数据矩阵604的形状可以被格式化，诸如以适应阵列606的任何任意配置的列和行。另外，在已知权重数据矩阵604的情况下，则可以在不使用格式器的情况下以向量化格式生成并存储行620。
在实施例中，图6中的点积630是通过将对应于列610的向量与对应于行620的向量进行点乘来生成的。在实施例中，如图7所示，可以通过将对应于列612的向量与对应于行620的向量进行点乘来获得下一点积632。如本领域技术人员将认识到的，一旦阵列606的第一行中的所有点积都被填充，阵列606的第二行的点积可以通过将输入数据矩阵602的第一列610中的元素与权重数据矩阵604的第二行进行点乘等来计算。
重要的是要注意，图6至图8仅用于说明性目的，并且可以同时执行上述点乘以生成单次矩阵-矩阵乘法操作。
图9图示了根据本公开的各种实施例的示例性去卷积操作。去卷积系统900包括输入图像902的输入通道IC、权重922、点积904906和输出通道OC。本领域技术人员将认识到，去卷积操作900实际上是卷积操作(例如，图5所示的卷积)的数学换位(近似求逆)。本领域技术人员将进一步认识到，可以通过应用与普通卷积神经网络类似的进程来使用神经网络学习去卷积操作900。为了简洁起见，此处不再重复与图5类似的组件的描述或功能。
在实施例中，图9中的去卷积操作900通过使用权重922解构点积904 906来重新组装矩阵912。与卷积操作一样，去卷积900可以为每个输入通道IC使用不同的权重集合922。在实施例中，去卷积900可以有利地应用于图像以执行图像去卷积，例如以提高针对伪像的鲁棒性。其他应用可以包括图像数据的分析和恢复等。
图10图示了根据本公开的各种实施例的用于执行算术运算以加速卷积神经网络的过程。
当从第一逻辑电路接收到可以表示数据矩阵中的行的第一操作数集合时，用于执行算术运算的过程1000从步骤1002开始。可以对第一操作数集合进行向量化，使得这些操作数与矩阵处理器中的输入对齐。在某些实施例中，向量化的操作数的大小直接与沿轴线到矩阵处理器的输入数目相关。
在步骤1004，从第二逻辑电路接收可以表示权重矩阵中的列的第二操作数集合。可以对该第二操作数集合进行向量化，使得这些操作数在矩阵处理器中的对应输入内对齐。在某些实施例中，向量化的操作数的大小直接与沿不同轴线到矩阵处理器的输入数目相关。
在步骤1006，将第一操作数集合与第二操作数集合进行点乘以获得一个或多个点积。在某些实施例中，跨操作数集合的该集合操作在单个时钟周期中执行。
在步骤1008，点积可以用于利用滤波器对图像进行卷积，以产生卷积结果。
在步骤1010，进一步处理卷积结果以增强图像输出。可以使用非线性函数、归一化操作或池化操作来进行该进一步处理。
本领域技术人员将认识到，任何计算系统或编程语言对于实践本发明来说都不重要。本领域技术人员还将认识到，上述许多元件可以在物理和/或功能上分离为子模块或组合在一起。
应该注意的是，以下权利要求的元素可以被不同地布置，包括具有多个相关性、配置和组合。例如，在实施例中，各种权利要求的主题可以与其他权利要求组合。
本领域技术人员将了解，前述示例和实施例是示例性的，并且不限制本发明的范围。其意图是，对本领域技术人员而言，在阅读说明书和研究附图之后显而易见的所有排列、增强、等效物、组合和改进都包括在本发明的真正精神和范围内。

Claims (21)

1.一种用于加速神经网络中的卷积的矩阵处理器，所述矩阵处理器包括：
第一输入电路，以二维阵列的第一维度被布置，所述第一输入电路被耦合以从第一逻辑电路接收N个操作数，所述N个操作数根据与所述第一维度相关的第一宽度而被格式化；
第二输入电路，以所述二维阵列的第二维度被布置，所述第二输入电路被耦合以从第二逻辑电路接收M个操作数，所述M个操作数根据与所述第二维度相关的第二宽度而被格式化；以及
多个子电路，被耦合以接收所述N个操作数和所述M个操作数，所述多个子电路的至少子集合包括算术逻辑单元、累加器和影子寄存器，所述子电路被耦合在所述二维阵列内，以对所述N个操作数和所述M个操作数执行算术运算。
2.根据权利要求1所述的矩阵处理器，其中所述算术运算是与卷积操作相关联的点积计算。
3.根据权利要求2所述的矩阵处理器，其中所述算术逻辑单元包括用以生成所述点积的乘加电路。
4.根据权利要求1所述的矩阵处理器，其中所述N个操作数表示图像数据，并且所述M个操作数表示权重值。
5.根据权利要求1所述的矩阵处理器，其中所述子电路中的至少一些子电路包括编码元件，所述编码元件被配置为对表示所述M个操作数中的一个或多个操作数的值进行编码。
6.根据权利要求5所述的矩阵处理器，其中所述编码元件是booth编码器。
7.根据权利要求1所述的矩阵处理器，其中所述N个操作数从数据输入矩阵被格式化。
8.根据权利要求1所述的矩阵处理器，进一步包括状态机，所述状态机使用滤波器大小和步幅中的至少一项来确定所述N个操作数或所述M个操作数内的可重用操作数。
9.根据权利要求1所述的矩阵处理器，其中加速的处理速度通过减少来自高速缓存的读取操作、并且经由所述多个子电路的加速的数据吞吐量而被实现。
10.一种用于加速神经网络中的卷积的系统，所述系统包括：
第一逻辑电路，生成N个操作数；
第一输入电路，以二维阵列的第一维度被布置，所述第一输入电路被耦合以从所述第一逻辑电路接收所述N个操作数；
第二逻辑电路，生成M个操作数；
第二输入电路，以所述二维阵列的第二维度被布置，所述第二输入电路被耦合以从所述第二逻辑电路接收M个操作数；
矩阵处理器，包括多个子电路，所述多个子电路被配置为执行所述N个操作数和所述M个操作数的点乘以生成点积；以及
输出阵列，被耦合至所述二维阵列，所述二维阵列被配置为使用所述点积以生成结果。
11.根据权利要求10所述的系统，其中所述N个操作数从数据输入矩阵被格式化为第一向量，并且所述M个操作数从权重输入矩阵被格式化为第二向量。
12.根据权利要求11所述的系统，其中所述第一逻辑电路包括存储所述N个操作数的多个数据寄存器，所述多个数据寄存器具有与所述二维阵列的所述第一维度相对应的第一宽度，并且所述第二逻辑电路包括存储所述M个权重操作数的多个权重寄存器，所述多个权重寄存器具有与所述二维阵列的所述第二维度相对应的第二宽度。
13.根据权利要求12所述的系统，其中所述第一宽度与生成所述结果的多个周期相对应。
14.根据权利要求12所述的系统，其中所述数据寄存器和所述权重寄存器仅被访问一次，以分别获取第一数目的元素和第二数目的元素。
15.根据权利要求10所述的系统，其中所述子电路包括影子寄存器，所述影子寄存器被配置为在一个或多个时钟周期中将数据移动到移位寄存器。
16.根据权利要求10所述的系统，进一步包括缓冲器，所述缓冲器被耦合至所述数据输入矩阵和所述权重输入矩阵中的至少一个矩阵，所述缓冲器存储最近使用的数据的副本，以使得能够重用而无需在后续周期中重新获取。
17.根据权利要求10所述的系统，其中所述结果是与滤波器到图像的区域的应用相对应的输出矩阵。
18.根据权利要求10所述的系统，进一步包括状态机，所述状态机使用滤波器大小和步幅中的至少一项来标识可重用数据。
19.一种用于使用矩阵乘法电路来使卷积神经网络更快的方法，所述方法包括：
从第一逻辑电路接收表示数据矩阵中的行的第一操作数集合；
从第二逻辑电路接收表示权重矩阵中的列的第二操作数集合；
将所述第一操作数集合与所述第二操作数集合进行点乘以获得一个或多个点积；以及
使用所述点积来利用滤波器对图像进行卷积，以产生卷积结果。
20.根据权利要求19所述的方法，其中对所述图像进行卷积包括：通过卷积层处理所述一个或多个点积以生成层输出。
21.根据权利要求20所述的方法，其中生成所述层输出包括：将非线性函数、归一化和池化中的一项应用于所述卷积结果。
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