KR980005551A - Method of forming a contact hole in a semiconductor device - Google Patents

Method of forming a contact hole in a semiconductor device Download PDF

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Publication number
KR980005551A
KR980005551A KR1019960024543A KR19960024543A KR980005551A KR 980005551 A KR980005551 A KR 980005551A KR 1019960024543 A KR1019960024543 A KR 1019960024543A KR 19960024543 A KR19960024543 A KR 19960024543A KR 980005551 A KR980005551 A KR 980005551A
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KR
South Korea
Prior art keywords
silicon substrate
wave
plasma
summer
damaged
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Application number
KR1019960024543A
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Korean (ko)
Inventor
백현철
김광철
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019960024543A priority Critical patent/KR980005551A/en
Publication of KR980005551A publication Critical patent/KR980005551A/en

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Abstract

본 발명은 반도체 소자의 콘택홀 형성방법을 개시한다. 개시된 본 발명의 반도체 소자의 콘택홀 형성 방법은 콘택 에칭 공정으로 인하여 손상된 실리콘 기판의 깊이 및 제거될 실리콘 기판의 손상된 깊이를 설정하기 위하여 서머 웨이브 측정 장비를 사용하여 베어(Bare) 실리콘 기판의 서머 웨이브를 측정하는 단계; 서머 웨이브를 측정한 베어 실리콘 기판을 콘택 에칭시 사용할 장비 및 공정 조건으로 플라즈마에 노출시키는 단계; 플라즈마에 노출이 완료된 실리콘 기판을 서머 웨이브 측정시 바람직하지 않은 노이즈 요인을 제거하도록 세정을 실시한 후, 서머 웨이브 값을 측정하는 단계; 세정후에 서머 웨이브 값이 측정된 실리콘 기판을 PET조건으로 플라즈마에 노출시키는 단계; PET조건으로 플라즈마에 노출된 실리콘 기판을 일정 두께 단위로 에칭하는 단계; 및 PET를 이용하여 일정 두께 단위로 에칭하면서 베어 실리콘 기판의 서머 웨이브 값으로부터 세정후 실리콘 기판의 서머 웨이브 값을 매번 측정하여 손상된 기판의 깊이 및 손상된 층을 제거하는데 필요한 시간으로 설정하는 단계를 포함하는 것을 특징으로 한다.The present invention discloses a method for forming a contact hole in a semiconductor device. A method of forming a contact hole in a semiconductor device of the present invention includes forming a contact hole on a bare silicon substrate using a summer wave measurement equipment to set a depth of a damaged silicon substrate and a damaged depth of the silicon substrate to be removed due to a contact etching process, ; Exposing the bare silicon substrate having the measured solar wave to a plasma using equipment and process conditions to be used for contact etching; Cleaning the silicon substrate having been exposed to the plasma to remove an undesirable noise factor in the measurement of the summer wave, and then measuring the value of the summer wave; Exposing the silicon substrate having the measured value of the summer wave to the plasma in the PET condition after cleaning; Etching the silicon substrate exposed to the plasma under the PET condition in a predetermined thickness unit; And measuring the summer wave value of the silicon substrate after cleaning from the summer wave value of the bare silicon substrate while etching with a certain thickness unit using PET to set the depth of the damaged substrate and the time required to remove the damaged layer .

Description

반도체 소자의 콘택홀 형성 방법Method of forming a contact hole in a semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1도는 본 발명의 실시예에 따른 인가된 전압에 대한 서머 웨이브의 변화를 나타낸 그래프.FIG. 1 is a graph showing a variation of a summer wave with respect to an applied voltage according to an embodiment of the present invention; FIG.

Claims (2)

콘택 에칭 공정으로 인하여 손상된 실리콘 기판의 깊이 및 제거될 실리콘 기판의 손상된 층의 깊이를 설정하기 위하여 서머 웨이브 측정 장비를 사용하여 베어(Bare) 실리콘 기판의 서머 웨이브를 측정하는 단계; 서머 웨이브를 측정한 베어 실리콘 기판을 콘택 에칭시 사용할 장비 및 공정 조건으로 플라즈마에 노출시키는 단계; 플라즈마에 노출이 완료된 실리콘 기판을 서머 웨이브 측정시 바람직하지 않은 노이즈 요인을 제거하도록 세정을 실시한 후, 서머 웨이브 값을 측정하는 단계; 세정후에 서머 웨이브 값이 측정된 실리콘 기판을 PET조건으로 플라즈마에 노출시키는 단계; PET조건으로 플라즈마에 노출된 실리콘 기판을 일정 두께 단위로 에칭하는 단계; 및 PET를 이용하여 일정 두께 단위로 에칭하면서 베어 실리콘 기판의 서머 웨이브 값으로부터 세정후 실리콘 기판의 서머 웨이브 값을 매번 측정하여 손상된 기판의 깊이 및 손상된 층을 제거하는데 필요한 시간으로 설정하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성 방법.Measuring a summer wave of a bare silicon substrate using a summer wave measuring instrument to set the depth of the damaged silicon substrate and the depth of the damaged layer of the silicon substrate to be removed due to the contact etching process; Exposing the bare silicon substrate having the measured solar wave to a plasma using equipment and process conditions to be used for contact etching; Cleaning the silicon substrate having been exposed to the plasma to remove an undesirable noise factor in the measurement of the summer wave, and then measuring the value of the summer wave; Exposing the silicon substrate having the measured value of the summer wave to the plasma in the PET condition after cleaning; Etching the silicon substrate exposed to the plasma under the PET condition in a predetermined thickness unit; And measuring the summer wave value of the silicon substrate after cleaning from the summer wave value of the bare silicon substrate while etching with a certain thickness unit using PET to set the depth of the damaged substrate and the time required to remove the damaged layer Wherein the contact hole is formed on the semiconductor substrate. 제1항에 있어서, 상기 실리콘 기판을 플라즈마에 노출하는 노출 시간은 오버에치(Overetch) 시간만으로 하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성 방법.The method of claim 1, wherein the exposure time for exposing the silicon substrate to the plasma is made only by an overetch time. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960024543A 1996-06-27 1996-06-27 Method of forming a contact hole in a semiconductor device KR980005551A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960024543A KR980005551A (en) 1996-06-27 1996-06-27 Method of forming a contact hole in a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960024543A KR980005551A (en) 1996-06-27 1996-06-27 Method of forming a contact hole in a semiconductor device

Publications (1)

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KR980005551A true KR980005551A (en) 1998-03-30

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KR1019960024543A KR980005551A (en) 1996-06-27 1996-06-27 Method of forming a contact hole in a semiconductor device

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