KR970077486A - Trench device isolation method of semiconductor device - Google Patents

Trench device isolation method of semiconductor device Download PDF

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Publication number
KR970077486A
KR970077486A KR1019960016259A KR19960016259A KR970077486A KR 970077486 A KR970077486 A KR 970077486A KR 1019960016259 A KR1019960016259 A KR 1019960016259A KR 19960016259 A KR19960016259 A KR 19960016259A KR 970077486 A KR970077486 A KR 970077486A
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South Korea
Prior art keywords
trench
buffer layer
stress buffer
layer pattern
forming
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KR1019960016259A
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Korean (ko)
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KR0183854B1 (en
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이한신
박문한
신유균
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김광호
삼성전자 주식회사
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Publication of KR970077486A publication Critical patent/KR970077486A/en
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Publication of KR0183854B1 publication Critical patent/KR0183854B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 반도체 장치의 트렌치 소자 분리 방법에 관한 것으로, 본 발명에서는 반도체 장치의 소자 분리를 위하여 반도체 기판 상에 스트레스 완충층 및 식각 방지층을 차례대로 적층하고, 상기 반도체 기판의 소자분리 영역이 노출되도록 상기 식각 방지층 및 스트레스 온충층을 패터닝함으로써 식각 방지층 패턴 및 스트레스 완충층 패턴을 형성고, 상기 스트레스 완충층 패턴의 노출된 측벽을 습식 식각에 의해 일부 식각하여 언더컷을 형성하고, 사이 식각 방지층 패턴을 마스크로 하여 상기 반도체 기판을 소정의 깊이로 식각하여 트렌치를 형성하는 단계를 포함한다. 본 발명에 의하여, 비교적 단순한 공정에 의해 트렌치의 코너 부분이 라운딩됨으로써, 반도체 장치에서 험프 현상 및 역협폭 효과가 발생하는 것을 효과적으로 방지할 수 있다.The present invention relates to a trench device isolation method for a semiconductor device, in which a stress buffer layer and an etching prevention layer are sequentially stacked on a semiconductor substrate in order to isolate elements of the semiconductor device, Forming an etch stop layer pattern and a stress buffer layer pattern by patterning the etch stop layer and the stress relief layer, forming an undercut by partially etching the exposed side walls of the stress buffer layer pattern by wet etching, And etching the semiconductor substrate to a predetermined depth to form a trench. According to the present invention, the corner portions of the trench are rounded by a relatively simple process, thereby effectively preventing the hump phenomenon and the reverse narrowing effect from occurring in the semiconductor device.

Description

반도체 장치의 트렌치 소자 분리 방법Trench device isolation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제6도는 내지 제9도는 본 발명의 바람직한 실시예에 따른 반도체 장치의 트렌치 소자 분리방법을 설명하기 위한 단면도들이다.FIG. 6 through FIG. 9 are cross-sectional views for explaining a trench device isolation method of a semiconductor device according to a preferred embodiment of the present invention.

Claims (6)

반도체 기판 상에 스트레스 완충층 및 식각 방지층을 차례대로 적층하는 단계와, 상기 반도체 기판의 소자 분리 영역이 노출되도록 상기 식각 방지층 스트레스 완충층을 패터닝함으로써 식각 방지용 패턴 및 스트레스 완충층 패턴을 형성하는 단계와, 상기 스트레스 완충층 패턴의 노출된 측벽을 습식 식각에 의해 일부식각하여 언더켓을 형성하는 단계와, 상기 식각 방지층 패턴을 마스크로 하여 상기 반도체 기판을 소정의 깊이로 식각하여 트렌치를 형성하는 단계와, 상기 트렌치의 측벽에 산화막을 형성하는 단계와, 상기 트렌치를 메립히기 위한 절연 물질을 증착하는 단계와, 상기 식각 방지층 패턴이 노출될 때가지 상기 절연 물질으 CMP(Chemical Mechanical Polishing)공정을 이용하여 평탄화하는 단계와, 상기 식각 방지층 패턴 및 스트레스 완충층 패턴을 차례로 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 트렌치 소자 분리 방법.Forming a stress buffer layer and a stress buffer layer on the semiconductor substrate in this order; patterning the etch stop layer stress buffer layer so as to expose the element isolation region of the semiconductor substrate to form an etching prevention pattern and a stress buffer layer pattern; Forming a trench by etching the semiconductor substrate to a predetermined depth using the etch stop layer pattern as a mask, forming a trench by etching the exposed side wall of the buffer layer pattern by wet etching to form an undercut, Forming an oxide film on the sidewall of the trench; depositing an insulating material for burying the trench; and planarizing the insulating material using a chemical mechanical polishing (CMP) process until the etch stop layer pattern is exposed , The etch stop layer pattern and the stress buffer layer pattern And removing the trenches in order. 제1항에 있어서, 상기 트렌치 측벽에 산화막을 형성하는 단계는 습식 산화 분위기 또는 건식 산화 분위기에서 행하는 것을 특징으로 하는 반도체 장치의 트렌치 소자 분리 방법.The method according to claim 1, wherein the step of forming the oxide film on the sidewall of the trench is performed in a wet oxidation atmosphere or a dry oxidation atmosphere. 제1항에 있어서, 상기 스트레스 완충층은 열산화막으로 형성하는 것을 특징으로 하는 반도체 장치의 트렌치 소자 분리 방법.The method of claim 1, wherein the stress buffer layer is formed of a thermal oxide film. 제1항에 있어서, 상기 식각 방지층은 질화막으로 형성하는 것을 특징으로 하는 반도체 장치의 트렌치 소자 분리 방법.The method according to claim 1, wherein the etch stop layer is formed of a nitride film. 제1항에 있어서, 상기 트렌치를 매립하기 위한 절연 물질은 CVD(Chemical Vapor Deosition)에 의해 증착된 산화막으로 형성하는 것을 특징으로하는 반도체 장치의 트렌치 소자 분리 방법The trench isolation method of claim 1, wherein the insulating material for filling the trench is formed of an oxide film deposited by CVD (Chemical Vapor Deposition). 반도체 기판 상에 스트레스 완충층 및 식각 방지층 차례대로 적층하는 단계와, 상기 반도체 기판의 소자 분리 영역이 노출되도록 상기 식각 방지층 및 스트레스 완충층을 패너닝함으로써 식각 방지층 패턴 및 스트레스 완충층 패턴을 형성하는 단계와, 상기 식각 방지층 패턴을 마스크로 하여 상기 반도체 기판을 소정의 깊이로 식각하여 트렌치를 형성하는 단계와, 상기 스트레스 완층층 패턴의 노출된 측벽을 습식 식각에 의해 일부 식각하여 언더컷을 형성하는 단계와, 상기 트렌치의 측벽에 산화막을 형성하는 단계와, 상기 트렌치를 매립하기 위한 절연 물질을 증착하는 단계와, 상기 식각 방지층 패턴이 노출될 때까지 상기 절연물질을 CMP공정을 이용하여 평탄화하는 단계와, 상기 식각 방지층 패턴 및 스트레스 완충층 패턴을 차례로 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 트렌치 소자 분리 방법Forming an etching prevention layer pattern and a stress buffer layer pattern by patterning the etching prevention layer and the stress buffer layer so as to expose an element isolation region of the semiconductor substrate; forming a stress buffer layer and a stress buffer layer on the semiconductor substrate in this order; Forming a trench by etching the semiconductor substrate to a predetermined depth using the etch stop layer pattern as a mask; forming an undercut by partially etching the exposed sidewall of the stress complete layer pattern by wet etching; Depositing an insulating material to fill the trench; and planarizing the insulating material using a CMP process until the etch stop layer pattern is exposed, Pattern and stress buffer layer pattern Separation trench of a semiconductor device comprising the method ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960016259A 1996-05-15 1996-05-15 Trench element isolation method of semiconductor element KR0183854B1 (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010038753A (en) * 1999-10-27 2001-05-15 박종섭 Manufacturing method for isolation in semiconductor device
KR100317041B1 (en) * 1999-10-18 2001-12-22 윤종용 A method of forming a trench isolation in a semiconductor device
KR100359858B1 (en) * 1998-12-30 2003-01-15 주식회사 하이닉스반도체 Method of forming device isolation film in semiconductor device
KR100381399B1 (en) * 1999-07-27 2003-04-23 닛뽕덴끼 가부시끼가이샤 Manufacture of semiconductor device
KR100382722B1 (en) * 2000-11-09 2003-05-09 삼성전자주식회사 Trench isolation layer and manufacturing method thereof
KR100548586B1 (en) * 1998-08-28 2006-04-06 주식회사 하이닉스반도체 Trench manufacturing method of semiconductor device

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100451494B1 (en) * 1998-10-29 2004-12-03 주식회사 하이닉스반도체 Device Separating Method of Semiconductor Device
KR100564423B1 (en) * 1999-07-02 2006-03-28 주식회사 하이닉스반도체 Formation method for isolation layer of semiconductor device
JP2002203894A (en) * 2001-01-04 2002-07-19 Mitsubishi Electric Corp Method for manufacturing semiconductor device
KR20040000682A (en) * 2002-06-25 2004-01-07 동부전자 주식회사 Method for forming isolation layer of semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100548586B1 (en) * 1998-08-28 2006-04-06 주식회사 하이닉스반도체 Trench manufacturing method of semiconductor device
KR100359858B1 (en) * 1998-12-30 2003-01-15 주식회사 하이닉스반도체 Method of forming device isolation film in semiconductor device
KR100381399B1 (en) * 1999-07-27 2003-04-23 닛뽕덴끼 가부시끼가이샤 Manufacture of semiconductor device
KR100317041B1 (en) * 1999-10-18 2001-12-22 윤종용 A method of forming a trench isolation in a semiconductor device
KR20010038753A (en) * 1999-10-27 2001-05-15 박종섭 Manufacturing method for isolation in semiconductor device
KR100382722B1 (en) * 2000-11-09 2003-05-09 삼성전자주식회사 Trench isolation layer and manufacturing method thereof

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Publication number Publication date
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