KR20010038753A - Manufacturing method for isolation in semiconductor device - Google Patents
Manufacturing method for isolation in semiconductor device Download PDFInfo
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- KR20010038753A KR20010038753A KR1019990046865A KR19990046865A KR20010038753A KR 20010038753 A KR20010038753 A KR 20010038753A KR 1019990046865 A KR1019990046865 A KR 1019990046865A KR 19990046865 A KR19990046865 A KR 19990046865A KR 20010038753 A KR20010038753 A KR 20010038753A
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- oxide film
- substrate
- trench
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- oxide layer
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- 238000002955 isolation Methods 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title abstract description 14
- 238000004519 manufacturing process Methods 0.000 title abstract description 11
- 150000004767 nitrides Chemical class 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 18
- 238000000206 photolithography Methods 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims description 24
- 238000000926 separation method Methods 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체 장치의 분리구조 제조방법에 관한 것으로, 특히 얕은 트랜치형 분리구조에서, 그 분리구조의 측면부가 하드마스크 식각시 식각되어 트랜치 상부측의 기판의 첨점이 노출되는 것을 방지하는데 적당하도록 한 반도체 장치의 분리구조 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a separation structure of a semiconductor device, particularly in shallow trench type isolation structures, in which side surfaces of the isolation structure are etched during hard mask etching to prevent exposure of the substrates on the trench upper side. A method for manufacturing a separated structure of a semiconductor device.
도1a 내지 도1c는 종래 반도체 장치의 분리구조 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 패드산화막(2)과 질화막(3)을 순차적으로 증착하고, 상기 질화막(3)의 상부에 포토레지스트(PR)를 도포하고, 노광 및 현상하여 상기 질화막(3)의 상부일부를 노출시키는 패턴을 형성하고, 그 패턴이 형성된 포토레지스트(PR)를 식각마스크로 사용하는 식각공정으로 상기 노출된 질화막(3), 패드산화막(2), 기판(1)을 차례로 식각하여 상기 기판(1)에 트랜치를 형성하는 단계(도1a)와; 상기 구조의 상부전면에 산화막(4)을 증착하고, 평탄화하여 상기 트랜치 내에 위치하는 분리구조를 형성하는 단계(도1b)와; 상기 산화막(4)의 평탄화로 노출되는 질화막(3)을 제거하고, 노출되는 패드산화막(2)을 제거하는 단계(도1c)로 구성된다.1A to 1C are cross-sectional views of a process for fabricating a separate structure of a conventional semiconductor device. As shown therein, a pad oxide film 2 and a nitride film 3 are sequentially deposited on an upper portion of a substrate 1, and the nitride film 3 Photoresist (PR) is applied on the upper part of the), exposed and developed to form a pattern to expose the upper portion of the nitride film (3), the etching process using the photoresist (PR) having the pattern as an etching mask Etching the exposed nitride film 3, the pad oxide film 2, and the substrate 1 in order to form a trench in the substrate 1 (FIG. 1A); Depositing an oxide film (4) on the top surface of the structure and planarizing to form a separation structure located in the trench (FIG. 1B); Removing the nitride film 3 exposed by planarization of the oxide film 4, and removing the exposed pad oxide film 2 (Fig. 1C).
이하, 상기와 같은 종래 반도체 장치의 분리구조 제조방법을 좀 더 상세히 설명한다.Hereinafter, a method of manufacturing a separation structure of a conventional semiconductor device as described above will be described in more detail.
먼저, 도1a에 도시한 바와 같이 기판(1)의 상부에 패드산화막(2)과 질화막(3)을 순차적으로 증착한다.First, as shown in FIG. 1A, the pad oxide film 2 and the nitride film 3 are sequentially deposited on the substrate 1.
그 다음, 상기 질화막(3)의 상부에 포토레지스트(PR)를 증착하고, 노광 및 현상하여 상기 질화막(3)의 일부영역을 노출시키는 패턴을 형성한다.Next, a photoresist PR is deposited on the nitride film 3, and exposed and developed to form a pattern for exposing a portion of the nitride film 3.
그 다음, 상기 패턴이 형성된 포토레지스트(PR)를 식각마스크로 사용하는 식각공정으로 상기 노출되어 있는 질화막(3)과 그 하부측의 패드산화막(2)을 순차적으로 식각하여 기판(1)의 일부영역을 노출시킨다.Subsequently, a part of the substrate 1 is etched by sequentially etching the exposed nitride film 3 and the pad oxide film 2 on the lower side thereof by an etching process using the photoresist PR having the pattern as an etching mask. Expose the area.
그 다음, 상기 노출된 기판(1)을 건식식각하여 상기 기판(1)에 트랜치를 형성한다.Then, the exposed substrate 1 is dry etched to form a trench in the substrate 1.
그 다음, 도1b에 도시한 바와 같이 상기 구조의 상부전면에 산화막(4)을 상기 형성한 트랜치가 채워질정도로 두껍게 증착하고, 그 증착된 산화막(4)의 상부로 부터 평탄화를 실시하여 상기 질화막(3)의 상부면이 노출될 때까지 평탄화공정을 실시한다.Then, as shown in FIG. 1B, the oxide film 4 is deposited on the upper surface of the structure so as to fill the trench, and the planarized from the top of the deposited oxide film 4 is planarized. The planarization process is performed until the upper surface of 3) is exposed.
이와 같은 평탄화공정으로 상기 질화막(3)이 노출됨과 아울러 트랜치내에 산화막(4)인 분리구조가 잔존하게 되어 분리구조를 형성하게 된다.In this planarization process, the nitride film 3 is exposed and the isolation structure of the oxide film 4 remains in the trench to form the isolation structure.
그 다음, 도1c에 도시한 바와 같이 상기 잔존하는 질화막(3)과 그 하부의 패드산화막(2)을 식각한다.Then, as shown in Fig. 1C, the remaining nitride film 3 and the pad oxide film 2 below it are etched.
이때, 상기 질화막(3)과 패드산화막(2)의 식각공정으로 상기 형성된 분리구조의 상부 또한 식각되며, 그 분리구조의 중앙부보다 측면부에서 식각량이 많아 상기 트랜치의 측면상부인 기판(1)의 첨점부가 노출된다.At this time, the upper part of the formed isolation structure is also etched by the etching process of the nitride film 3 and the pad oxide film 2, and the amount of etching is greater at the side portion than the center portion of the isolation structure, and the peaks of the substrate 1, which is on the side of the trench, are etched. The part is exposed.
상기한 바와 같이 종래 반도체 장치의 분리구조 제조방법은 하드마스크를 이용하여 트랜치를 형성하고, 그 트랜치내에 위치하는 분리구조를 형성한 후, 다시 하드마스크를 식각하는 공정을 수행하여 상기 하드마스크 식각공정에서 분리구조의 측면부가 식각되어 분리구조의 측면상부측 기판영역이 노출됨으로써, 전계의 집중에 의해 누설전류가 발생하게 되어 반도체 장치의 특성을 열화시키는 문제점이 있었다.As described above, a method of manufacturing a separation structure of a conventional semiconductor device includes forming a trench using a hard mask, forming a separation structure located in the trench, and then etching the hard mask again to perform etching of the hard mask. Since the side portion of the isolation structure is etched to expose the substrate region on the upper side of the isolation structure, leakage current is generated by concentration of an electric field, thereby deteriorating characteristics of the semiconductor device.
이와 같은 문제점을 감안한 본 발명은 기판의 첨점부가 노출되는 것을 방지하는 반도체 장치의 분리구조 제조방법을 제공함에 그 목적이 있다.It is an object of the present invention to provide a method of manufacturing a separate structure of a semiconductor device which prevents the pointed portion of a substrate from being exposed.
도1a 내지 도1c는 종래 반도체 장치의 분리구조 제조공정 수순단면도.1A to 1C are cross-sectional views of a process for manufacturing a separate structure of a conventional semiconductor device.
도2a 내지 도2d는 본 발명 반도체 장치의 분리구조 제조공정 수순단면도.2A to 2D are cross-sectional views of a process for manufacturing a separation structure of a semiconductor device of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
1:기판 2:패드산화막1: Substrate 2: Pad oxide film
3:질화막 4,5:산화막3: nitride film 4, 5: oxide film
상기와 같은 목적은 기판의 상부에 패드산화막과 질화막을 순차적으로 증착하고, 사진식각공정을 통해 상기 질화막, 패드산화막, 기판의 일부영역을 식각하여 상기 기판의 일부에 트랜치를 형성하는 단계와; 상기 구조의 상부전면에 측벽형성용 산화막을 증착하는 단계와; 상기 구조의 상부전면에 분리구조 형성용 산화막을 상기 트랜치가 채워질정도로 증착하고, 그 증착된 분리구조 형성용 산화막을 평탄화하여 상기 질화막의 측면에 측벽형성용 산화막을 잔존시켜 산화막 측벽을 형성함과 아울러 트랜치 내에 잔존하는 분리구조 형성용 산화막인 분리구조를 형성하는 단계와; 상기 노출된 질화막을 식각하고, 기판의 상부에 증착된 패드산화막을 식각하여 기판의 상부를 노출시키는 단계로 구성함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The above object is to sequentially deposit a pad oxide film and a nitride film on the substrate, and to form a trench in a portion of the substrate by etching a portion of the nitride film, the pad oxide film and the substrate through a photolithography process; Depositing an oxide film for forming a sidewall on an upper surface of the structure; Depositing an oxide film for forming an isolation structure on the upper surface of the structure to the extent that the trench is filled, and planarizing the deposited oxide film for forming the isolation structure to leave an oxide film for forming a sidewall on the side of the nitride film to form an oxide film sidewall. Forming a separation structure that is an oxide film for forming a separation structure remaining in the trench; It is achieved by etching the exposed nitride film, and etching the pad oxide film deposited on the substrate to expose the upper portion of the substrate, which will be described in detail with reference to the accompanying drawings. .
도2a 내지 도2d는 본 발명 반도체 장치의 분리구조 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 패드산화막(2)과 질화막(3)을 증착하고, 사진식각공정을 통해 상기 질화막(3), 패드산화막(2), 기판(1)의 일부영역을 식각하여 상기 기판(1)에 트랜치를 형성하는 공정(도2a)과; 상기 구조의 상부전면에 산화막(4)을 증착하는 단계(도2b)와; 상기 구조의 상부전면에 산화막(5)을 상기 트랜치가 채워질정도로 증착하고, 평탄화하여 상기 질화막(3)의 측면에 산화막(4) 측벽을 형성함과 아울러 트랜치 내에 잔존하는 산화막(5)인 분리구조를 형성하는 단계(도2c)와; 상기 노출된 질화막(3)을 식각하고, 기판(1)의 상부에 증착된 패드산화막(2)을 식각하여 기판(1)의 상부를 노출시키는 단계(도2d)로 이루어진다.2A to 2D are cross-sectional views of a process for manufacturing a separate structure of the semiconductor device according to the present invention. As shown therein, a pad oxide film 2 and a nitride film 3 are deposited on an upper portion of a substrate 1, and a photolithography process is performed. Etching a portion of the nitride film 3, the pad oxide film 2, and the substrate 1 to form a trench in the substrate 1 (FIG. 2A); Depositing an oxide film (4) on the top surface of the structure (FIG. 2B); An oxide film 5 is deposited on the upper surface of the structure to the extent that the trench is filled and planarized to form a sidewall of the oxide film 4 on the side of the nitride film 3, and an oxide film 5 remaining in the trench. Forming (Fig. 2c); The exposed nitride film 3 is etched, and the pad oxide film 2 deposited on the substrate 1 is etched to expose the upper portion of the substrate 1 (FIG. 2D).
이하, 상기와 같이 구성된 본 발명 반도체 장치의 분리구조 제조방법을 좀 더 상세히 설명한다.Hereinafter, a method of manufacturing a separate structure of the semiconductor device of the present invention configured as described above will be described in more detail.
먼저, 도2a에 도시한 바와 같이 기판(1)의 상부전면에 패드산화막(2)을 증착하고, 그 패드산화막(2)의 상부에 질화막(3)을 증착한다.First, as shown in FIG. 2A, a pad oxide film 2 is deposited on the upper surface of the substrate 1, and a nitride film 3 is deposited on the pad oxide film 2.
그 다음, 상기 질화막(3)의 상부에 포토레지스트(PR)를 도포하고, 노광 및 현상하여 상기 질화막(3)의 상부일부를 노출시키는 패턴을 형성한다.Next, a photoresist PR is coated on the nitride film 3, and exposed and developed to form a pattern exposing a portion of the upper portion of the nitride film 3.
그 다음, 패턴이 형성된 포토레지스트(PR)를 식각마스크로 사용하는 식각공정으로 상기 노출된 질화막(3)을 식각하고, 그 질화막(3)의 식각으로 노출되는 패드산화막(2)을 식각하여 기판(1)의 일부영역을 노출시킨다.Subsequently, the exposed nitride film 3 is etched by using a patterned photoresist PR as an etching mask, and the pad oxide film 2 exposed by etching the nitride film 3 is etched to form a substrate. Partial area of (1) is exposed.
그 다음, 상기 노출된 기판(1)을 건식식각하여 소정깊이의 트랜치를 형성한다.Then, the exposed substrate 1 is dry etched to form a trench having a predetermined depth.
그 다음, 도2b에 도시한 바와 같이 상기 트랜치가 형성된 기판(1)과 질화막(3)의 전면에 산화막(4)을 증착한다. 이때 증착하는 산화막(4)은 상기 트랜치를 채우는 것이아니며, 상기 질화막(3)의 측면에 측벽을 형성할 수 있을 정도의 두께로만 증착한다.Next, as shown in FIG. 2B, an oxide film 4 is deposited on the entire surface of the substrate 1 and nitride film 3 on which the trench is formed. At this time, the deposited oxide film 4 does not fill the trench, but is deposited only to a thickness sufficient to form sidewalls on the side surfaces of the nitride film 3.
그 다음, 도2c에 도시한 바와 같이 상기 산화막(4)의 상부전면에 상기 트랜치가 모두 채워질수 있도록 두꺼운 산화막(5)을 증착한다.Next, as shown in FIG. 2C, a thick oxide film 5 is deposited on the upper surface of the oxide film 4 so that the trenches can be filled.
그 다음, 상기 증착된 산화막(5)의 상부표면으로 부터 평탄화를 실시하여 상기 질화막(3)의 상부가 노출될 때까지 진행한다.Then, planarization is performed from the upper surface of the deposited oxide film 5 until the upper part of the nitride film 3 is exposed.
상기의 평탄화공정으로 상기 기판(1)에 형성한 트랜치 내에는 산화막(5)이 잔존하게 되어 분리구조를 형성하며, 상기 질화막(3)의 측면에는 식각되지 않은 산화막(4)이 잔존하게 된다. 즉, 상기 분리구조의 상부측면에 산화막(4)이 돌출된 형태를 갖게 된다.The oxide film 5 remains in the trench formed in the substrate 1 by the planarization process to form a separation structure, and the etched oxide film 4 remains on the side surface of the nitride film 3. That is, the oxide film 4 protrudes from the upper side surface of the separation structure.
그 다음, 도2d에 도시한 바와 같이 상기 노출된 질화막(3)을 식각함과 아울러 그 질화막(3)의 식각으로 노출되는 패드산화막(2)을 제거하여 트랜치가 형성되지 않은 기판(1)의 상부를 노출시킨다.Next, as shown in FIG. 2D, the exposed nitride film 3 is etched and the pad oxide film 2 exposed by the etching of the nitride film 3 is removed to remove the trench 1. Expose the top.
이때의 식각공정으로 상기 분리구조인 산화막(5)의 상부측면부에 잔존하는 산화막(4)과 그 분리구조인 산화막(5)의 상부측 또한 식각되며, 상기 산화막(4)이 분리구조의 상부측면부에 위치하여 그 분리구조의 측면부가 과도 식각되는 것을 방지하여 상기 트랜치의 측면상부인 기판(1)의 첨점부가 노출되는 것을 방지할 수 있게 된다.In this etching process, the oxide film 4 remaining in the upper side surface portion of the oxide film 5 as the separation structure and the upper side of the oxide film 5 as the separation structure are also etched, and the oxide film 4 is at the upper side portion of the separation structure. It can be prevented from over-etching the side portion of the separation structure to be exposed to the peak portion of the substrate (1) that is on the side of the trench.
상기한 바와 같이 본 발명은 분리구조의 측면상부인 하드마스크의 측면에 산화막 측벽을 형성하여, 상기 하드마스크의 식각시 분리구조의 측면부가 과도하게 식각되는 것을 방지함으로써, 분리구조의 측면상부측 기판인 기판의 첨점부가 노출되어 누설전류가 발생하는 것을 방지하여 반도체 장치의 특성열화를 방지하는 효과가 있다.As described above, the present invention forms sidewalls of an oxide film on the side of the hard mask, which is on the side of the separation structure, thereby preventing the side portions of the separation structure from being excessively etched during the etching of the hard mask, thereby preventing the substrate from being excessively etched. There is an effect of preventing the deterioration of the characteristics of the semiconductor device by preventing the leakage of the leakage current generated by the exposed portion of the phosphorus substrate.
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| KR100615593B1 (en) * | 2004-05-06 | 2006-08-25 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device with recess channel |
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| KR970060450A (en) * | 1996-01-31 | 1997-08-12 | 김광호 | Method of separating semiconductor device using trench |
| KR970077486A (en) * | 1996-05-15 | 1997-12-12 | 김광호 | Trench device isolation method of semiconductor device |
| KR19980025838A (en) * | 1996-10-05 | 1998-07-15 | 김광호 | Method of forming device isolation film in semiconductor device |
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| KR100615593B1 (en) * | 2004-05-06 | 2006-08-25 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device with recess channel |
| US7232727B2 (en) | 2004-05-06 | 2007-06-19 | Hynix Semiconductor, Inc. | Method for fabricating semiconductor device with recessed channel region |
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