KR20010084524A - Method for forming isolation region of semiconductor device - Google Patents
Method for forming isolation region of semiconductor device Download PDFInfo
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- KR20010084524A KR20010084524A KR1020000009631A KR20000009631A KR20010084524A KR 20010084524 A KR20010084524 A KR 20010084524A KR 1020000009631 A KR1020000009631 A KR 1020000009631A KR 20000009631 A KR20000009631 A KR 20000009631A KR 20010084524 A KR20010084524 A KR 20010084524A
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- trench
- semiconductor substrate
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- film
- oxide film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000002955 isolation Methods 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 150000004767 nitrides Chemical class 0.000 claims abstract description 20
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 7
- 239000010408 film Substances 0.000 claims description 54
- 238000000151 deposition Methods 0.000 claims description 7
- 239000010409 thin film Substances 0.000 claims description 7
- 238000005498 polishing Methods 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 2
- 238000000206 photolithography Methods 0.000 claims description 2
- 239000011800 void material Substances 0.000 abstract description 5
- 230000010354 integration Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체소자의 격리영역 형성방법에 관한 것으로, 특히 고집적화에 따른 트렌치 격리영역의 적용에 있어서, 평탄화가 실시된 다음 트렌치 폭이 넓은 영역의 단차문제 및 폭이 좁은 영역의 보이드문제를 해결하기에 적당하도록 한 반도체소자의 격리영역 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an isolation region of a semiconductor device. In particular, in the application of the trench isolation region according to high integration, after the planarization is performed, a step problem of a wide trench width and a void problem of a narrow width region are solved. The present invention relates to a method for forming an isolation region of a semiconductor device suitable for use.
일반적으로, 반도체소자가 고집적화됨에 따라 소자간 전기적 격리를 위해 트렌치가 적용되고 있으며, 이와같은 종래 반도체소자의 격리영역 형성방법을 첨부한 도1a 내지 도1d의 수순단면도를 참조하여 상세히 설명하면 다음과 같다.In general, as semiconductor devices are highly integrated, trenches have been applied for electrical isolation between devices. A detailed description will now be made with reference to the procedure cross-sectional view of FIGS. 1A to 1D attached to a method of forming an isolation region of a conventional semiconductor device. same.
먼저, 도1a에 도시한 바와같이 반도체기판(1)의 상부에 산화막(2)과 질화막(3)을 순차적으로 형성한다. 이때, 산화막(2)은 반도체기판(1)이 질화막(3)과 직접 접촉함에 따라 손상되는 것을 완충하는 버퍼로 적용된다.First, as shown in FIG. 1A, an oxide film 2 and a nitride film 3 are sequentially formed on the semiconductor substrate 1. At this time, the oxide film 2 is applied as a buffer to buffer the semiconductor substrate 1 from being damaged by the direct contact with the nitride film 3.
그리고, 도1b에 도시한 바와같이 상기 질화막(3)의 상부에 감광막(PR1)을 도포하고, 노광 및 현상하여 감광막(PR1) 패턴을 형성한 다음 질화막(3)과 산화막(2)을 순차적으로 식각하여 소자간 격리영역이 형성될 반도체기판(1)을 노출시킨다. 이때, 소자간 격리영역은 제조되는 반도체소자에서 요구되는 바에 따라 폭이 넓은 영역과 폭이 좁은 영역이 형성될 수 있다.As shown in FIG. 1B, the photoresist film PR1 is coated on the nitride film 3, exposed and developed to form a photoresist film PR1 pattern, and the nitride film 3 and the oxide film 2 are sequentially formed. Etching exposes the semiconductor substrate 1 on which the isolation regions are formed. In this case, the isolation region between the devices may be a wide region and a narrow region as required by the semiconductor device to be manufactured.
그리고, 도1c에 도시한 바와같이 상기 감광막(PR1) 패턴을 제거하고, 상기 질화막(3)을 하드마스크(hard mask)로 적용하여 반도체기판(1)을 소정의 깊이로 식각함으로써, 트렌치를 형성한 다음 상부전면에 고온저압 산화막(4)을 증착하여 트렌치를 채운다. 이때, 트렌치의 폭이 넓은 영역은 인접하는 영역에 비해 상대적으로 단차가 낮고, 폭이 좁은 영역은 고온저압 산화막(4)의 스텝-커버리지(step coverage) 특성에 따라 보이드가 형성된다.As shown in FIG. 1C, the photoresist film PR1 pattern is removed, and the trench is formed by etching the semiconductor substrate 1 to a predetermined depth by applying the nitride film 3 as a hard mask. Then, a high temperature low pressure oxide film 4 is deposited on the upper surface to fill the trench. At this time, the wide area of the trench has a lower step than the adjacent area, and the narrow area has voids according to the step coverage characteristic of the high temperature low pressure oxide film 4.
그리고, 도1d에 도시한 바와같이 상기 고온저압 산화막(4)을 화학기계적 연마(chemical mechanical polishing : CMP)하여 평탄화한 다음 상기 질화막(3)과 산화막(2)을 순차적으로 제거한다. 이때, 상기 트렌치의 폭이 넓은 영역은 패턴의 크기, 조밀한 정도에 따라 연마되는 양이 상이한 화학기계적 연마의 특성으로 인해 주변영역에 비해 단차가 낮아지며, 폭이 좁은 영역의 경우에는 보이드가 노출된다.As shown in FIG. 1D, the high temperature low pressure oxide film 4 is planarized by chemical mechanical polishing (CMP), and then the nitride film 3 and the oxide film 2 are sequentially removed. At this time, the wide area of the trench has a lower step compared to the surrounding area due to the characteristics of chemical mechanical polishing in which the amount of polishing is different depending on the size and density of the pattern, and the void is exposed in the narrow area. .
상술한 바와같이 종래 반도체소자의 격리영역 형성방법은 트렌치의 폭이 넓은 경우에는 화학기계적 연마의 특성으로 인해 주변영역에 비해 단차가 낮아지고, 또한 폭이 좁은 경우에는 보이드가 노출되어 소자간 격리특성을 저하시키는 문제점이 있었다.As described above, in the method of forming an isolation region of a conventional semiconductor device, when the width of the trench is wide, the step is lower than the peripheral region due to the characteristics of chemical mechanical polishing, and in the case of the narrow width, the voids are exposed to expose the isolation characteristics between the devices. There was a problem of lowering.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 고집적화에 따른 트렌치 격리영역의 적용에 있어서, 평탄화가 실시된 다음 트렌치 폭이 넓은 영역의 단차문제 및 폭이 좁은 영역의 보이드문제를 해결할 수 있는 반도체소자의 격리영역 형성방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to apply a trench isolation region according to high integration, and to achieve a step problem and a width difference in a wide trench width after planarization. The present invention provides a method of forming an isolation region of a semiconductor device that can solve a void problem of a narrow region.
도1a 내지 도1d는 종래 반도체소자의 격리영역 형성방법을 보인 수순단면도.1A to 1D are cross-sectional views showing a method of forming an isolation region of a conventional semiconductor device.
도2a 내지 도2f는 본 발명의 일 실시예를 보인 수순단면도.2a to 2f are cross-sectional views showing an embodiment of the present invention.
***도면의 주요부분에 대한 부호의 설명****** Explanation of symbols for main parts of drawing ***
11:반도체기판 12:산화막11: semiconductor substrate 12: oxide film
13:질화막 14,16:고온저압 산화막13: Nitride film 14, 16: High temperature low pressure oxide film
15:BPSG막15: BPSG film
상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자의 격리영역 형성방법은 반도체기판 상부에 산화막과 질화막을 형성한 다음 사진식각을 통해 소자간 격리영역을 패터닝할 수 있는 질화막의 하드마스크를 형성하는 공정과; 상기 질화막의 하드마스크를 통해 반도체기판을 식각하여 트렌치를 형성한 다음 상부전면에 박막의 제1고온저압 산화막을 증착하는 공정과; 상기 제1고온저압 산화막이 증착된 결과물의 상부전면에 후막의 BPSG막을 증착하여 트렌치를 채운 다음 반도체기판의 표면보다 단차가 낮아지도록 에치-백(etch-back)하는 공정과; 상기 결과물의 상부전면에 박막의 제2고온저압 산화막을 반도체기판의 표면보다 단차가 높아지도록 증착하여 트렌치를 채우고, 화학기계적 연마를 통해 평탄화한 다음 질화막과 산화막을 제거하는 공정을 구비하여 이루어지는 것을 특징으로 한다.In the method of forming an isolation region of a semiconductor device as described above, an oxide film and a nitride film are formed on an upper portion of a semiconductor substrate, and then a hard mask of a nitride film capable of patterning the isolation region between devices through photolithography is formed. Process of doing; Forming a trench by etching the semiconductor substrate through the hard mask of the nitride film, and then depositing a first high temperature low pressure oxide film of a thin film on an upper surface thereof; Depositing a thick BPSG film on the upper surface of the resultant product on which the first high temperature and low pressure oxide film is deposited to fill the trench, and then etching back to lower the step than the surface of the semiconductor substrate; And depositing a second high temperature and low pressure oxide film of the thin film on the upper surface of the resultant so as to have a step higher than the surface of the semiconductor substrate to fill the trench, and planarizing through chemical mechanical polishing, and then removing the nitride film and the oxide film. It is done.
상기한 바와같은 본 발명에 의한 반도체소자의 격리영역 형성방법을 첨부한 도2a 내지 도2f의 수순단면도를 일 실시예로 하여 상세히 설명하면 다음과 같다.Referring to FIG. 2A through FIG. 2F, which are attached to the method for forming an isolation region of a semiconductor device according to the present invention as described above, the procedure is described in detail as follows.
먼저, 도2a에 도시한 바와같이 종래의 도1a 및 도1b의 공정을 진행함으로써, 반도체기판(11) 상부에 산화막(12)과 질화막(13)이 적층된 하드마스크를 형성하여 소자간 격리영역이 형성될 반도체기판(11)을 노출시킨다.First, as shown in FIG. 2A, by performing the processes of FIGS. 1A and 1B according to the related art, a hard mask in which an oxide film 12 and a nitride film 13 are stacked on the semiconductor substrate 11 is formed to form an isolation region between devices. The semiconductor substrate 11 to be formed is exposed.
그리고, 도2b에 도시한 바와같이 상기 노출된 반도체기판(11)을 식각하여 트렌치를 형성한 다음 상부전면에 박막의 고온저압 산화막(14)을 증착한다. 이때, 고온저압 산화막(14)을 형성하는 이유는 후속 BPSG막(15)의 증착으로 인해 붕소나 인이 반도체기판(11)으로 확산되는 것을 방지하기 위해서이다.As shown in FIG. 2B, the exposed semiconductor substrate 11 is etched to form a trench, and then a high temperature low pressure oxide film 14 of a thin film is deposited on the upper surface. At this time, the reason for forming the high temperature low pressure oxide film 14 is to prevent diffusion of boron or phosphorus into the semiconductor substrate 11 due to the deposition of the subsequent BPSG film 15.
그리고, 도2c에 도시한 바와같이 상기 박막의 고온저압 산화막(14)의 상부전면에 후막의 BPSG막(15)을 증착하여 트렌치를 채운다.As shown in FIG. 2C, a thick BPSG film 15 is deposited on the upper surface of the high temperature low pressure oxide film 14 of the thin film to fill the trench.
그리고, 도2d에 도시한 바와같이 상기 BPSG막(15)을 반도체기판(11)의 표면보다 단차가 낮아지도록 마스크를 쓰지 않는 블랭킷(balnket) 에치-백한다. 이때, 질화막(13)의 상부에 형성된 고온저압 산화막(14)도 제거된다.As shown in FIG. 2D, the BPSG film 15 is etched-back of a blanket without a mask so that the step is lower than the surface of the semiconductor substrate 11. At this time, the high temperature low pressure oxide film 14 formed on the nitride film 13 is also removed.
그리고, 도2e에 도시한 바와같이 상기 결과물의 상부전면에 박막의 고온저압 산화막(16)을 반도체기판(11)의 표면보다 단차가 높아지도록 증착하여 트렌치를 채운다.As shown in FIG. 2E, the high temperature low pressure oxide film 16 of the thin film is deposited on the upper surface of the resultant so as to have a step higher than the surface of the semiconductor substrate 11 to fill the trench.
그리고, 도2f에 도시한 바와같이 상기 고온저압 산화막(16)을 화학기계적 연마하여 평탄화한 다음 질화막(13)과 산화막(12)을 순차적으로 제거한다.As shown in FIG. 2F, the high temperature low pressure oxide film 16 is chemically polished and planarized, and then the nitride film 13 and the oxide film 12 are sequentially removed.
상기한 바와같은 본 발명에 의한 반도체소자의 격리영역 형성방법은 고집적화에 따른 트렌치 격리영역의 적용에 있어서, 평탄화가 실시된 다음 트렌치 폭이 넓은 영역의 단차문제 및 폭이 좁은 영역의 보이드문제를 해결하여 소자간 격리특성을 향상시킬 수 있는 효과가 있다.As described above, in the method of forming the isolation region of the semiconductor device according to the present invention, in the application of the trench isolation region according to the high integration, after the planarization, the problem of the step difference in the wide trench region and the void problem in the narrow region are solved. Therefore, there is an effect that can improve isolation characteristics between devices.
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| KR100701692B1 (en) * | 2005-04-15 | 2007-03-29 | 주식회사 하이닉스반도체 | Method for forming isolation layer of semiconductor device |
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|---|---|---|---|---|
| JPH0846024A (en) * | 1994-07-26 | 1996-02-16 | Toshiba Microelectron Corp | Manufacture of semiconductor device |
| KR0165462B1 (en) * | 1995-10-28 | 1999-02-01 | 김광호 | Method of trench isolation |
| KR0183738B1 (en) * | 1995-09-14 | 1999-04-15 | 김광호 | Element isolation method of semiconductor device |
| JPH11297811A (en) * | 1998-03-31 | 1999-10-29 | Internatl Business Mach Corp <Ibm> | Manufacture of semiconductor device |
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2000
- 2000-02-26 KR KR1020000009631A patent/KR20010084524A/en not_active Application Discontinuation
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0846024A (en) * | 1994-07-26 | 1996-02-16 | Toshiba Microelectron Corp | Manufacture of semiconductor device |
| KR0183738B1 (en) * | 1995-09-14 | 1999-04-15 | 김광호 | Element isolation method of semiconductor device |
| KR0165462B1 (en) * | 1995-10-28 | 1999-02-01 | 김광호 | Method of trench isolation |
| JPH11297811A (en) * | 1998-03-31 | 1999-10-29 | Internatl Business Mach Corp <Ibm> | Manufacture of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100701692B1 (en) * | 2005-04-15 | 2007-03-29 | 주식회사 하이닉스반도체 | Method for forming isolation layer of semiconductor device |
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