KR19990081301A - Trench element isolation formation method of semiconductor device - Google Patents

Abstract

A method of forming trench isolation in a semiconductor device is disclosed. One aspect of the present invention forms a polishing stop layer on a semiconductor substrate. The abrasive barrier layer is made of nitride or oxynitride. A mask layer is formed on the polishing stop layer. The mask layer and the polishing stop layer are patterned to form a mask layer pattern and a polishing stop layer pattern exposing a portion of the semiconductor substrate. A portion of the semiconductor substrate exposing the mask layer pattern as an etching mask is etched to form a trench. The sidewalls of the polishing stopper layer pattern are selectively etched using the mask layer pattern as an etch mask to form an abrasive stopper layer pattern having recessed sidewalls. An insulating layer filling the trench is formed. The insulating layer is polished using the polishing stop layer pattern with the sidewall recessed as an end point of polishing to form an insulating layer pattern covering the edge of the trench. Polishing is performed by a chemical mechanical polishing method. The sidewalls remove the recessed abrasive layer pattern.

Description

Trench element isolation formation method of semiconductor device

TECHNICAL FIELD The present invention relates to semiconductor devices, and more particularly, to a method of forming trench isolation.

In the process of manufacturing a semiconductor device, there is a process of forming element isolation. The LOCOS (LOCal Oxidation of Silicon) process has been mainly used to form device isolation, but the field of device isolation due to the reduction of active area due to bird's beak and the reduction of device separation distance Problems such as silicon defects due to thinning of the oxide layer and stress occurring in the oxidation process of the field oxide layer have been derived. In addition to these problems, as the semiconductor devices are highly integrated, the use of trench isolation processes is increasing.

1 schematically illustrates a conventional trench device isolation method.

Specifically, in the conventional trench device isolation method, after the trench 15 is formed in the semiconductor substrate 10, the sidewall oxide layer 17 for curing is formed on the inner wall of the trench 15. After the trench 15 is filled with an insulating layer by CVD oxide or the like deposited by Chemical Vapor Deposition (hereinafter referred to as "CVD") method, the insulating layer is polished. In this case, the polishing is performed by Chemical Mechanical Polishing (hereinafter referred to as "CMP") method, and the polishing uses a polishing stop layer (CMP stopper) formed on the semiconductor substrate 10 as an end point of polishing. . The polishing stop layer is removed after patterning the insulating layer to form an insulating layer pattern 20 filling the trench. In this case, the polishing barrier layer is removed by wet etching.

The insulating layer pattern 20 may be violated by the wet etching. The insulating layer pattern 20 is mainly formed of CVD oxide. The CVD oxide has a very high etching rate compared with thermal oxide by wet etching. Accordingly, a loss of the insulating layer pattern 20 may occur due to the wet etching. In particular, the loss is likely to occur at the edge of the trench 15 and a recess A occurs in the edge of the trench 15. Such grooves A are frequently generated by wet etching processes, such as a photoresist layer strip or pre deffusion cleaning process, which are accompanied by a photolithography process performed after the device isolation process. do.

The phenomenon in which the grooves A occur at the edges of the trench 15 is called a field edge recess, which is a threshold current voltage curve of the semiconductor substrate 10. Can generate a double hump. Furthermore, deterioration of gate characteristics, inverse narrow width, or the like may cause deterioration of characteristics of semiconductor devices.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method for forming isolation of trenches in a semiconductor device capable of preventing occurrence of field edge recesses.

1 is a cross-sectional view schematically illustrating a conventional method of forming trench isolation.

2 to 7 are cross-sectional views schematically illustrating a method of forming isolation of trench elements according to an embodiment of the present invention.

One aspect of the present invention for achieving the above technical problem is to form a polishing stop layer on a semiconductor substrate. The polishing barrier layer is made of nitride or oxynitride. A mask layer is formed on the polishing stop layer. The mask layer and the polishing stop layer are patterned to form a mask layer pattern and a polishing stop layer pattern exposing a portion of the semiconductor substrate. A portion of the semiconductor substrate exposing the mask layer pattern as an etching mask is etched to form a trench. The sidewalls of the polishing stopper layer pattern may be selectively etched using the mask layer pattern as an etch mask to form an abrasive stopper layer pattern having recessed sidewalls. An insulating layer filling the trench is formed. The insulating layer is polished using the polishing stop layer pattern having the sidewall recessed as an end point of polishing to form an insulating layer pattern covering the edge of the trench. The polishing is performed by a chemical mechanical polishing method. The sidewalls remove the recessed abrasive layer pattern.

According to the present invention, it is possible to prevent the occurrence of field edge recesses.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the thicknesses of layers in the drawings and the like are exaggerated for clarity, and the elements denoted by the same reference numerals in the drawings mean the same elements. Also, if a layer is described as being on or in contact with another layer or semiconductor substrate, the layer may be in direct contact with the other layer or semiconductor substrate, or between the third A layer may be interposed.

2 to 7 are cross-sectional views schematically illustrating a method of forming isolation of trench elements according to an embodiment of the present invention.

2 schematically illustrates a step of forming an abrasive stop layer 300 and a mask layer 400 on a semiconductor substrate 100.

Specifically, a pad oxide layer 200 is formed on the semiconductor substrate 100. Next, when polishing, such as CMP, is performed on the pad oxide layer 200, the polishing stop layer 300 used as an end point of polishing is formed. The polishing barrier layer 300 may be formed of nitride, oxynitride, or the like. Next, a mask layer 400 is formed on the polishing stopper layer 300 by using an oxide or the like.

FIG. 3 schematically illustrates a step of forming the trench 150 using the mask layer pattern 450 as an etch mask.

Specifically, the mask layer 400 and the polishing stop layer pattern 350 exposing a part of the semiconductor substrate 100 by sequentially patterning the mask layer 400 and the polishing stop layer 300 by a photolithography process may be used. Form. Thereafter, a portion of the semiconductor substrate 100 that is exposed using the mask layer pattern 450 as an etch mask is etched to form the trench 150.

4 schematically illustrates forming an abrasive barrier layer pattern 355 with recessed sidewalls.

In detail, the sidewall of the polishing stopper layer pattern 300 is selectively etched using the mask layer pattern 450 as an etching mask to form the polishing stopper layer pattern 355 having the sidewall recessed therein. That is, the sidewalls of the portion where the mask layer pattern 450 and the polishing stop layer pattern 355 contact each other are under cut. In this case, the recessed amount is related to the amount of the insulating layer pattern filling the trench 150 formed thereafter is consumed by a process of removing the polishing stop layer pattern 355 after the device isolation process or a subsequent wet etching process. I set it. Preferably the amount of recesses is set equal to the amount consumed thereafter.

5 schematically illustrates a step of forming an insulating layer 500 filling the trench 150.

Specifically, sidewall oxidation is performed to form sidewall oxide layers 170 on the inner walls of the trenches 150 to remove defects generated during the formation of the trenches 150 or to alleviate stress. . Thereafter, the insulating layer 500 filling the trench 150 is formed using CVD oxide or the like. In this case, the insulating layer 500 fills the recessed portion of the sidewall of the polishing stop layer pattern 355 to cover the edge of the trench 150.

6 schematically illustrates a step of polishing the insulating layer 500 to form the insulating layer pattern 550.

Specifically, the insulating layer 500 is polished by CMP or the like. In this case, the polishing stop layer pattern 355 is used as an end point of the CMP. The insulating layer pattern 550 formed by the polishing covers the edge of the trench 150. Thereafter, the polishing stop layer pattern 355 is removed by a wet etching method or the like. In this case, the edge portion of the trench 150 is protected by the insulating layer pattern 550. Thus, field edge recesses can be prevented from occurring.

FIG. 7 schematically illustrates a result of performing wet etching performed after the device isolation process.

Specifically, as described above, after the isolation layer pattern 550 is formed to implement device isolation, a wet etching process such as a photoresist layer strip or pre-diffusion cleaning is performed before the gate is formed. In this case, the edge of the trench 150 is protected by the insulating layer pattern 550 and is not intruded by the wet etching process. Therefore, no field edge recess occurs, thereby preventing double humps from occurring in the threshold current voltage curve of the semiconductor substrate 100. In addition, it is possible to prevent deterioration of characteristics of the semiconductor device such as deterioration of gate characteristics and inverse narrowing phenomenon.

As mentioned above, although this invention was demonstrated in detail through the specific Example, this invention is not limited to this, It is clear that the deformation | transformation and improvement are possible by the person of ordinary skill in the art within the technical idea of this invention.

According to the present invention described above, it is possible to prevent the field edge recesses from occurring. As a result, generation of double humps in the threshold current voltage curve of the semiconductor substrate can be suppressed, and deterioration in characteristics of the semiconductor device, such as deterioration of gate characteristics and inverse narrowing phenomenon, can be prevented.

Claims (3)

Forming an abrasive stop layer on the semiconductor substrate; Forming a mask layer on the polishing stop layer; Patterning the mask layer and the polishing stop layer to form a mask layer pattern and a polishing stop layer pattern exposing a portion of the semiconductor substrate; Etching a portion of the semiconductor substrate exposing the mask layer pattern with an etch mask to form a trench; Selectively etching sidewalls of the polishing barrier layer pattern using the mask layer pattern as an etch mask to form a polishing barrier layer pattern having recessed sidewalls; Forming an insulating layer filling the trench; Polishing the insulating layer using the polishing stop layer pattern having the sidewall recessed as an end point of polishing to form an insulating layer pattern covering an edge of the trench; And And removing the polishing stop layer pattern in which the sidewalls are recessed. The method of claim 1, wherein the polishing barrier layer is formed of nitride or oxynitride. The method of claim 1, wherein the polishing is performed by a chemical mechanical polishing method.