KR970018356A - Device Separation Method of Semiconductor Device - Google Patents

Device Separation Method of Semiconductor Device Download PDF

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Publication number
KR970018356A
KR970018356A KR1019950029287A KR19950029287A KR970018356A KR 970018356 A KR970018356 A KR 970018356A KR 1019950029287 A KR1019950029287 A KR 1019950029287A KR 19950029287 A KR19950029287 A KR 19950029287A KR 970018356 A KR970018356 A KR 970018356A
Authority
KR
South Korea
Prior art keywords
trench
etch stop
stop layer
insulating material
forming
Prior art date
Application number
KR1019950029287A
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Korean (ko)
Inventor
신홍재
최지현
황병근
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950029287A priority Critical patent/KR970018356A/en
Publication of KR970018356A publication Critical patent/KR970018356A/en

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Abstract

트렌치를 이용한 반도체장치의 소자분리 방법에 대해 기재되어 있다.A device isolation method of a semiconductor device using a trench is described.

이는; 반도체 기판 상에 패드산화막 및 식각방지막 및 식각방지막을 차례로 적층하는 단계, 비활성영역의 상기 패드산화막 및 식각방지막을 식각하는 단계, 식각방지막을 마스크로하여 반도체 기판에 트렌치를 형성하는 단계, 트렌치의 내측벽에 스페이서를 형성하는 단계, 트렌치의 바닥을 산화시키는 단계 트렌치 내측벽의 스페이서를 제거하는 단계, 트렌치를 절연물질로 매립하는 단계 및 식각방지막의 표면이 드러날 때까지 상기 절연물질을 에치백하는 단계를 포함한다.this is; Stacking a pad oxide film, an etch stop layer and an etch stop layer on a semiconductor substrate in sequence, etching the pad oxide layer and an etch stop layer in an inactive region, forming a trench in the semiconductor substrate using the etch stop layer as a mask, and forming a trench in the trench Forming spacers in the sidewalls, oxidizing the bottom of the trench, removing spacers in the trench inner walls, embedding the trenches with insulating material and etching back the insulating material until the surface of the etch stop layer is revealed It includes.

따라서, 트렌치의 매립이 용이하고, 펀치쓰루 및 디슁현상의 발생을 억제할 수 있다.Therefore, the trench is easily buried and the occurrence of punch through and dip phenomenon can be suppressed.

Description

반도체장치의 소자 분리방법Device Separation Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 내지 제1E도는 본 발명의 일 실시예에 의한 반도체장치의 소자분리방법을 설명하기 위한 단면도들이다.1A to 1E are cross-sectional views illustrating a device isolation method of a semiconductor device in accordance with an embodiment of the present invention.

Claims (6)

반도체 기판 상에 패드산화막 및 식각방지막을 차례로 적층하는 단계; 비활성영역의 상기 패드산화막 및 식각방지막을 식각하는 단계; 상기 식각방지막을 마스크로하여 반도체 기판에 트렌치를 형성하는 단계; 상기 트렌티의 내측벽에 스페이서를 형성하는 단계; 상기 트렌치의 바닥을 산화시키는 단계; 상기 트렌치 내측벽의 스페이서를 제거하는 단계; 상기 트렌치를 절연물질로 매립하는 단계; 및 상기 식각방지막의 표면이 드러날 때까지 상기 절연물질을 에치백하는 단계를 포함하는 것을 특징으로 하는 반도체장치의 소자분리방법.Sequentially depositing a pad oxide film and an etch stop layer on the semiconductor substrate; Etching the pad oxide layer and the etch stop layer in the inactive region; Forming a trench in the semiconductor substrate using the etch stop layer as a mask; Forming a spacer on an inner wall of the trench; Oxidizing the bottom of the trench; Removing the spacers of the trench inner wall; Filling the trench with an insulating material; And etching back the insulating material until the surface of the etch stop layer is exposed. 제1항에 있어서, 상기 트렌치의 깊이를 얕은 접합(shallow junction)의 두께보다 크게 하는 것을 특징으로 하는 반도체 장치의 소자분리 방법.2. The method of claim 1 wherein the depth of the trench is greater than the thickness of a shallow junction. 제1항에 있어서, 상기 식각방지막 및 스페이서는 실리콘질화막으로 형성되는 것을 특징으로 하는 반도체장치의 소자분리 방법.The method of claim 1, wherein the etch stop layer and the spacer are formed of a silicon nitride layer. 제1항에 있어서, 상기 스페이서는 두께를 셀 영역의 트레티치 스페이서 크기의 1/2 이내로 하는 것을 특징으로 하는 반도체장치의 소자분리 방법.The method of claim 1, wherein the spacer has a thickness less than half the size of the trench spacer of the cell region. 제1항에 있어서, 상기 트렌치의 매립되는 절연막은 실리콘산화막으로 형성되는 것을 특징으로 하는 반도체장치의 소자분리 방법.2. The method of claim 1, wherein the insulating film embedded in the trench is formed of a silicon oxide film. 제1항에 있어서, 상기 절연물질을 에치백하는 단계는, 화확적-물리적 폴리슁(CMP)을 사용하여 이루어지는 것을 특징으로 하는 반도체장치의 소자분리 방법.The method of claim 1, wherein the etching back of the insulating material is performed using chemical-physical polysulfone (CMP).
KR1019950029287A 1995-09-07 1995-09-07 Device Separation Method of Semiconductor Device KR970018356A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950029287A KR970018356A (en) 1995-09-07 1995-09-07 Device Separation Method of Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950029287A KR970018356A (en) 1995-09-07 1995-09-07 Device Separation Method of Semiconductor Device

Publications (1)

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KR970018356A true KR970018356A (en) 1997-04-30

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KR1019950029287A KR970018356A (en) 1995-09-07 1995-09-07 Device Separation Method of Semiconductor Device

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100414024B1 (en) * 2001-05-09 2004-01-07 아남반도체 주식회사 Method for forming a isolation layer of trench type
KR100444315B1 (en) * 1997-06-28 2004-11-09 주식회사 하이닉스반도체 Method for manufacturing isolation layer with improved uniformity with active region of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100444315B1 (en) * 1997-06-28 2004-11-09 주식회사 하이닉스반도체 Method for manufacturing isolation layer with improved uniformity with active region of semiconductor device
KR100414024B1 (en) * 2001-05-09 2004-01-07 아남반도체 주식회사 Method for forming a isolation layer of trench type

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