KR970018369A - LOCOS-Trench Combination Device Isolation Method - Google Patents

LOCOS-Trench Combination Device Isolation Method Download PDF

Info

Publication number
KR970018369A
KR970018369A KR1019950031000A KR19950031000A KR970018369A KR 970018369 A KR970018369 A KR 970018369A KR 1019950031000 A KR1019950031000 A KR 1019950031000A KR 19950031000 A KR19950031000 A KR 19950031000A KR 970018369 A KR970018369 A KR 970018369A
Authority
KR
South Korea
Prior art keywords
trench
oxide film
semiconductor substrate
field oxide
filling
Prior art date
Application number
KR1019950031000A
Other languages
Korean (ko)
Inventor
안동호
홍수진
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950031000A priority Critical patent/KR970018369A/en
Publication of KR970018369A publication Critical patent/KR970018369A/en

Links

Landscapes

  • Element Separation (AREA)

Abstract

본 발명은 LOCOS와 트렌치를 조합한 반도체 장치의 소자분리 방법에 대해 기재되어 있다. 이는, 반도체기판 상에 패드산화막 및 질화막을 차례로 적층하는 공정, 비활성영역의 질화막 및 패드산화막을 식각하는 공정, 비활성영역에 필드산화막을 형성하는 공정, 필드산화막 에지부분의 반도체기판의 노출될 때까지 필드산화막을 식각하는 공정, 노출된 반도체기판을 식각함으로써 필드산화막 양측의 반도체 기판에 트렌치를 형성하는 공정, 트렌치를 절연물질로 매립하는 공정 및 적층된 막들을 제거하는 공정을 포함하여 이루어진다. 따라서, 종래의 LOCOS-트렌치 조합형의 소자분리 방법에 비해 공정을 단순화할 수 있으며, 사진식각 기술의 한계를 넘어 매우 좁은 폭의 트렌치도 형성할 수 있다.The present invention describes a device isolation method of a semiconductor device combining a LOCOS and a trench. This involves laminating a pad oxide film and a nitride film on a semiconductor substrate in sequence, etching a nitride film and a pad oxide film in an inactive region, forming a field oxide film in an inactive region, and exposing the semiconductor substrate at the edge portion of the field oxide film. Etching the field oxide film; forming a trench in the semiconductor substrate on both sides of the field oxide film by etching the exposed semiconductor substrate; embedding the trench with an insulating material; and removing the stacked films. Therefore, the process can be simplified compared to the conventional LOCOS- trench combination device isolation method, and it is possible to form a very narrow trench beyond the limitation of the photolithography technique.

Description

로코스(LOCOS)-트렌치 조합형 소자분리 방법LOCOS-Trench Combination Device Isolation Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제 2G도는 본 발명의 제1 실시예에 따른 로코스(LOCOS) - 트렌치 조합형 소자분리 방법을 설명하기 위한 단면도들이다.2A to 2G are cross-sectional views illustrating a LOCOS-trench combination device isolation method according to a first embodiment of the present invention.

Claims (5)

반돠체기판 상에 패드산화막 및 질화막을 차례로 적층하는 공정; 비활성영역의 상기 질화막 및 패드산화막을 실각하는 공정; 비활성영역에 필드산화막을 형성하는 공정; 필드산화막 에지부분의 반도체기판이 노출될 때가지 상기 필드산화막을 식각하는 공정; 노출된 반도체 기판을 식각함으로서 필드산화막 양측의 반도체 기판에 트렌치를 형성하는 공정; 상기 트렌치를 절연물질로 매립하는 공정; 및 적층된 막들을 제거하는 공정을 포함하는 것을 특징으로 하는 로코스(LOCOS)-트렌치 조합형 소자분리 방법.Stacking a pad oxide film and a nitride film on the semiconductor substrate one by one; Realizing the nitride film and the pad oxide film in an inactive region; Forming a field oxide film in an inactive region; Etching the field oxide layer until the semiconductor substrate at the edge portion of the field oxide layer is exposed; Forming trenches in the semiconductor substrates on both sides of the field oxide film by etching the exposed semiconductor substrate; Filling the trench with an insulating material; And a process of removing the stacked films. 제1항에 있어서, 상기 트렌치를 매립하는 공정은, 트렌치가 형성된 결과물에 열산화를 실시하는 공정으로 이루어지는 것을 특징으로 하는 로코스(LOCOS)-트렌치를 조합형 소자분리 방법.The method of claim 1, wherein the filling of the trench comprises a process of thermally oxidizing a resultant product in which the trench is formed. 제1항에 있어서, 상기 트렌치를 매립하는 공정은, 트렌치가 형성된 결과물 전면에, 상기 트렌치가 매립될 정도의 두께의 화학기상증착(CVD)법에 의한 산화막을 증착하는 공정, 및 상기 CVD산화막의 표면을 평탄화하는 공정으로 이루어지는 것을 특징으로 하는 로코스(LOCOS)-트렌치를 조합형 소자분리 방법.The method of claim 1, wherein the filling of the trench comprises depositing an oxide film by a chemical vapor deposition (CVD) method having a thickness such that the trench is buried on the entire surface of the trench formed product, and the CVD oxide film. A LOCOS trench comprising a step of planarizing the surface. 제3항에 있어서, 상기 CVD산화막의 표면을 평탄화하는 공정은 화학적 물리적 폴리슁 또는 에치백을 사용하여 진행되는 것을 특징으로 하는 로코스(LOCOS)-트렌치를 조합형 소자분리 방법.4. The method of claim 3, wherein the planarization of the surface of the CVD oxide film is performed using chemical physical polymers or etch backs. 제1항에 있어서, 상기 트렌치를 매립하는 공정은, 트렌치가 형성된 결과물 전면에 폴리실리콘을 증착하는 공정, 에치백에 의해 상기 트렌치를 매립하고, 트렌치의 상부에 스페이서를 형성하는 공정 및 상기 폴리실리콘을 산화시키는 공정으로 이루어지는 것을 특징으로 하는 로코스(LOCOS)-트렌치 조합형 소자분리 방법.The method of claim 1, wherein the filling of the trench comprises: depositing polysilicon on the entire surface of the trench formed product, filling the trench by etch back, and forming a spacer on the trench, and the polysilicon. LOCOS-trench combination device separation method characterized in that it comprises a step of oxidizing.
KR1019950031000A 1995-09-21 1995-09-21 LOCOS-Trench Combination Device Isolation Method KR970018369A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950031000A KR970018369A (en) 1995-09-21 1995-09-21 LOCOS-Trench Combination Device Isolation Method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950031000A KR970018369A (en) 1995-09-21 1995-09-21 LOCOS-Trench Combination Device Isolation Method

Publications (1)

Publication Number Publication Date
KR970018369A true KR970018369A (en) 1997-04-30

Family

ID=66615798

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950031000A KR970018369A (en) 1995-09-21 1995-09-21 LOCOS-Trench Combination Device Isolation Method

Country Status (1)

Country Link
KR (1) KR970018369A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100480625B1 (en) * 2002-10-24 2005-03-31 삼성전자주식회사 Method for forming trench isolation and semiconductor device comprising the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100480625B1 (en) * 2002-10-24 2005-03-31 삼성전자주식회사 Method for forming trench isolation and semiconductor device comprising the same

Similar Documents

Publication Publication Date Title
KR960043106A (en) Method of forming insulating film in semiconductor device
TW362256B (en) Isolation method in a semiconductor device
KR970013074A (en) Planarization method of semiconductor device and device isolation method using same
KR940016580A (en) Manufacturing Method of Semiconductor Device
KR970053384A (en) Method of forming device isolation region in semiconductor device
KR970053500A (en) Device Separating Method of Semiconductor Device
KR970063569A (en) Manufacturing Method of Semiconductor Device
KR970077486A (en) Trench device isolation method of semiconductor device
KR970018369A (en) LOCOS-Trench Combination Device Isolation Method
KR970072380A (en) Semiconductor device and manufacturing method thereof
KR950029850A (en) Field oxide film formation method of a semiconductor device
KR960015711A (en) SOI wafer manufacturing method using double stopper
KR20010008560A (en) Method For Forming The Isolation Layer Of Semiconductor Device
KR970018356A (en) Device Separation Method of Semiconductor Device
KR940002996A (en) Manufacturing Method of Semiconductor Device
KR970053383A (en) Trench device isolation method for semiconductor devices
KR970018363A (en) Locus and trench combination device isolation method of semiconductor device
KR970018365A (en) Device isolation method of semiconductor device
KR20000066937A (en) Method For Forming Field Oxide Layer Of Semiconductor Device
KR970067768A (en) Method of forming an element isolation region in a semiconductor device
KR970077484A (en) Method of forming an element isolation film of a semiconductor device
KR970053428A (en) Device Separation Method of Semiconductor Device
KR980006046A (en) Device Separation Method of Semiconductor Device
KR970053385A (en) Separation method of semiconductor device using trench
KR960032675A (en) Device Separator Formation Method

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination