KR980006063A - Device isolation method of semiconductor device - Google Patents
Device isolation method of semiconductor device Download PDFInfo
- Publication number
- KR980006063A KR980006063A KR1019960024508A KR19960024508A KR980006063A KR 980006063 A KR980006063 A KR 980006063A KR 1019960024508 A KR1019960024508 A KR 1019960024508A KR 19960024508 A KR19960024508 A KR 19960024508A KR 980006063 A KR980006063 A KR 980006063A
- Authority
- KR
- South Korea
- Prior art keywords
- spacer
- pattern
- etching
- semiconductor substrate
- film
- Prior art date
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Abstract
본 발명은 액티브 영역 및 표면 단차가 감소된 반도체 디바이스의 소자 분리방법을 개시한다. 본 발명의 소자 분리방법은 반도체 기판의 액티브 예정 영역에 제1 패턴을 형성하는 단계; 제1 패턴의 양측벽에 제1 패턴과 식각비가 상이한 물질의 스페이서를 형성하는 단계; 제1 패턴을 제거하는 단계; 스페이서가 충분히 매립되도록 스페이서와 식각비가 상이한 물질막을 증착하는 단계; 스페이서 상부 표면이 노출되도록 상기 물질막을 이방성 식각하는 단계; 스페이서를 제거하는 단계; 노출된 반도체 기판을 소정 깊이만큼 식각하여 트렌치를 형성하는 단계; 전체 구조물 상부에 절연막을 증착하는 단계; 반도체 기판의 표면이 노출되도록 에칭하여 트렌치내에 절연막을 매립식키는 단계를 포함하는 것을 특징으로 한다.The present invention discloses a device isolation method of a semiconductor device with reduced active region and surface step. A device isolation method of the present invention includes: forming a first pattern in an active predetermined region of a semiconductor substrate; Forming spacers of materials having different etch ratios from the first pattern on both sidewalls of the first pattern; Removing the first pattern; Depositing a material film having an etch rate different from that of the spacers so that the spacers are sufficiently filled; Anisotropically etching the material film so that the spacer upper surface is exposed; Removing the spacer; Etching the exposed semiconductor substrate by a predetermined depth to form a trench; Depositing an insulating film on the entire structure; Etching the surface of the semiconductor substrate so as to expose the surface of the semiconductor substrate so as to bury the insulating film in the trench.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.
제2a도 내지 제2g도는 본 발명의 반도체 디바이스의 소자 분리방법을 설명하기 위한 각 공정 순서별 단면도.FIGS. 2A to 2G are cross-sectional views for explaining a device isolation method of a semiconductor device according to the present invention; FIG.
Claims (7)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960024508A KR980006063A (en) | 1996-06-27 | 1996-06-27 | Device isolation method of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960024508A KR980006063A (en) | 1996-06-27 | 1996-06-27 | Device isolation method of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
KR980006063A true KR980006063A (en) | 1998-03-30 |
Family
ID=66240517
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019960024508A KR980006063A (en) | 1996-06-27 | 1996-06-27 | Device isolation method of semiconductor device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR980006063A (en) |
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1996
- 1996-06-27 KR KR1019960024508A patent/KR980006063A/en not_active Application Discontinuation
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E902 | Notification of reason for refusal | ||
E601 | Decision to refuse application |