KR980006063A - Device isolation method of semiconductor device - Google Patents

Device isolation method of semiconductor device Download PDF

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Publication number
KR980006063A
KR980006063A KR1019960024508A KR19960024508A KR980006063A KR 980006063 A KR980006063 A KR 980006063A KR 1019960024508 A KR1019960024508 A KR 1019960024508A KR 19960024508 A KR19960024508 A KR 19960024508A KR 980006063 A KR980006063 A KR 980006063A
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KR
South Korea
Prior art keywords
spacer
pattern
etching
semiconductor substrate
film
Prior art date
Application number
KR1019960024508A
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Korean (ko)
Inventor
구본성
이희기
김상철
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019960024508A priority Critical patent/KR980006063A/en
Publication of KR980006063A publication Critical patent/KR980006063A/en

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Abstract

본 발명은 액티브 영역 및 표면 단차가 감소된 반도체 디바이스의 소자 분리방법을 개시한다. 본 발명의 소자 분리방법은 반도체 기판의 액티브 예정 영역에 제1 패턴을 형성하는 단계; 제1 패턴의 양측벽에 제1 패턴과 식각비가 상이한 물질의 스페이서를 형성하는 단계; 제1 패턴을 제거하는 단계; 스페이서가 충분히 매립되도록 스페이서와 식각비가 상이한 물질막을 증착하는 단계; 스페이서 상부 표면이 노출되도록 상기 물질막을 이방성 식각하는 단계; 스페이서를 제거하는 단계; 노출된 반도체 기판을 소정 깊이만큼 식각하여 트렌치를 형성하는 단계; 전체 구조물 상부에 절연막을 증착하는 단계; 반도체 기판의 표면이 노출되도록 에칭하여 트렌치내에 절연막을 매립식키는 단계를 포함하는 것을 특징으로 한다.The present invention discloses a device isolation method of a semiconductor device with reduced active region and surface step. A device isolation method of the present invention includes: forming a first pattern in an active predetermined region of a semiconductor substrate; Forming spacers of materials having different etch ratios from the first pattern on both sidewalls of the first pattern; Removing the first pattern; Depositing a material film having an etch rate different from that of the spacers so that the spacers are sufficiently filled; Anisotropically etching the material film so that the spacer upper surface is exposed; Removing the spacer; Etching the exposed semiconductor substrate by a predetermined depth to form a trench; Depositing an insulating film on the entire structure; Etching the surface of the semiconductor substrate so as to expose the surface of the semiconductor substrate so as to bury the insulating film in the trench.

Description

반도체 디바이스의 소자 분리방법Device isolation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2a도 내지 제2g도는 본 발명의 반도체 디바이스의 소자 분리방법을 설명하기 위한 각 공정 순서별 단면도.FIGS. 2A to 2G are cross-sectional views for explaining a device isolation method of a semiconductor device according to the present invention; FIG.

Claims (7)

반도체 기판의 액티브 예정 영역에 제1 패턴을 형성하는 단계; 상기 제1 패턴의 양측벽에 제1 패턴과 식각비가 상이한 물질의 스페이서를 형성하는 단계; 상기 제1 패턴을 제거하는 단계; 상기 스페이서가 충분히 매립되도록 스페이서와 식각비가 상이한 물질막을 증착하는 단계; 상기 스페이서 상부 표면이 노출되도록 상기 스페이서와 식각비가 상이한 물질막을 이방성 식각하는 단계; 상기 스페이서를 제거하는 단계; 노출된 반도체 기판을 상기 스페이서와 식각비가 상이한 물질막을 마스크로 하여 소정 깊이만큼 식각하여 트렌치를 형성하는 단계; 전체 구조물 상부에 절연막을 증착하는 단계; 상기 반도체 기판의 표면이 노출되도록 에칭하여 트랜치내에 절연막을 매립시키는 단계를 포함하는 것을 특징으로 하는 반도체 디바이스 소자 분리방법.Forming a first pattern in an active predetermined region of the semiconductor substrate; Forming spacers of materials having different etch ratios from the first pattern on both sidewalls of the first pattern; Removing the first pattern; Depositing a material film having an etch rate different from that of the spacer so that the spacer is sufficiently filled; Anisotropically etching a material film having an etch rate different from that of the spacer so that the upper surface of the spacer is exposed; Removing the spacer; Forming a trench by etching the exposed semiconductor substrate to a predetermined depth using a material film having a different etching ratio from the spacer as a mask; Depositing an insulating film on the entire structure; And etching the exposed surface of the semiconductor substrate so as to fill the insulating film in the trench. 제1항에 있어서, 스페이서는 질화막으로 형성하는 것을 특징으로 하는 반도체 디바이스 소자 분리방법.The method according to claim 1, wherein the spacer is formed of a nitride film. 제1항에 있어서, 상기 제1 패턴은 습식 식각하여 제거하는 것을 특징으로 하는 반도체 디바이스 소자 분리방법.The method according to claim 1, wherein the first pattern is removed by wet etching. 제1항에 있어서, 상기 스페이서는 습식 식각방식에 의하여 제거하는 것을 특징으로 하는 반도체 디바이스 소자 분리방법.The method according to claim 1, wherein the spacer is removed by a wet etching method. 제1항에 있어서, 상기 트랜치내에 매립되는 절연막은 질화막인 것을 특징으로 하는 반도체 소자의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film buried in the trench is a nitride film. 제1항에 있어서, 상기 제1 패턴은 산화막으로 이루어지는 것을 특징으로 하는 반도체 디바이스 소자 분리방법.The method according to claim 1, wherein the first pattern is an oxide film. 제1항에 있어서, 상기 스페이서와 식각비가 다른 물질막은 산화막인 것을 특징으로 하는 반도체 디바이스 소자 분리방법.The method according to claim 1, wherein the material film having an etch rate different from that of the spacer is an oxide film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960024508A 1996-06-27 1996-06-27 Device isolation method of semiconductor device KR980006063A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960024508A KR980006063A (en) 1996-06-27 1996-06-27 Device isolation method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960024508A KR980006063A (en) 1996-06-27 1996-06-27 Device isolation method of semiconductor device

Publications (1)

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KR980006063A true KR980006063A (en) 1998-03-30

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KR1019960024508A KR980006063A (en) 1996-06-27 1996-06-27 Device isolation method of semiconductor device

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