KR970077773A - Trench device isolation method of semiconductor device - Google Patents

Trench device isolation method of semiconductor device Download PDF

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Publication number
KR970077773A
KR970077773A KR1019960016960A KR19960016960A KR970077773A KR 970077773 A KR970077773 A KR 970077773A KR 1019960016960 A KR1019960016960 A KR 1019960016960A KR 19960016960 A KR19960016960 A KR 19960016960A KR 970077773 A KR970077773 A KR 970077773A
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KR
South Korea
Prior art keywords
trench
semiconductor substrate
photoresist pattern
forming
isolation method
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Application number
KR1019960016960A
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Korean (ko)
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KR0183859B1 (en
Inventor
하대원
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김광호
삼성전자 주식회사
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Priority to KR1019960016960A priority Critical patent/KR0183859B1/en
Publication of KR970077773A publication Critical patent/KR970077773A/en
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Publication of KR0183859B1 publication Critical patent/KR0183859B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

딥핑 현상을 제거한 트렌치 소자분리방법에 대해 기재되어 있다.A trench element isolation method in which a dipping phenomenon is removed is described.

본 발명의 트렌치 소자분리방법은, 반도체기판에 소자형성영역과 소자분리영역을 정의하기 위한 소정의 포토레지스트 패턴을 형성하는 단계와, 상기 소자분리영역의 반도체기판을 산화시켜 소정두께의 산화막을 형성하는 단계와, 상기 포토레지스트 패턴의 둘레를 따라 상기 반도체기판에 대하여 식각선택비를 갖는 스페이서를 형성하는 단계와, 상기 포토레지스트 패턴 및 스페이서를 식각마스크로 적용하여 상기 반도체기판 내에 소정 깊이의 트렌치를 형성하는 단계와, 상기 트렌치에 절연물질을 채우는 단계를 구비하여 이루어진 것을 특징으로 한다. 따라서, 본 발명에 의한 트렌치 소자분리방법에 의하면, 소자형성영역과 소자분리영역을 경계 부분에 산화막이 남게 됨으로서, 종래 이 부분에서 발생되던 딥핑 현상을 제거할 수 있게 되어 소자의 신뢰성을 향상시킬 수 있게 된다.A trench isolation method according to the present invention includes the steps of forming a predetermined photoresist pattern for defining an element formation region and an element isolation region in a semiconductor substrate and forming an oxide film having a predetermined thickness by oxidizing the semiconductor substrate in the element isolation region Forming a spacer having an etch selectivity with respect to the semiconductor substrate along a periphery of the photoresist pattern; and applying a photoresist pattern and a spacer as an etch mask to form a trench having a predetermined depth in the semiconductor substrate And filling the trench with an insulating material. Therefore, according to the trench element isolation method of the present invention, since the oxide film remains at the boundary between the element formation region and the element isolation region, it is possible to remove the dipping phenomenon that has occurred in the conventional trench isolation method, .

Description

반도체장치의 트렌치 소자분리방법Trench device isolation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제3A도 내지 제3D도는 본 발명에 따른 트렌치 소자분리방법을 설명하기 위한 공정순서도이다.FIGS. 3A to 3D are process flow diagrams illustrating a trench device isolation method according to the present invention.

Claims (4)

반도체기판에 소자형성영역과 소자분리영역을 정의하기 위한 소정의 포토레지스트 패턴을 형성하는 단계; 상기 소자분리영역의 반도체기판을 산화시켜 소정두께의 산화막을 형성하는 단계; 상기 포토레지스트 패턴의 둘레를 따라 상기 반도체기판에 대하여 식각선택비를 갖는 스페이서를 형성하는 단계; 상기 포토레지스트 패턴 및 스페이서를 식각마스크로 적용하여 상기 반도체기판 내에 소정 깊이의 트렌치를 형성하는 단계; 및 상기 트렌치에 절연물질을 채우는 단계를 구비하여 이루어진 것을 특징으로 하는 트렌치 소자분리방법.Forming a predetermined photoresist pattern for defining an element formation region and an element isolation region in a semiconductor substrate; Oxidizing the semiconductor substrate in the device isolation region to form an oxide film having a predetermined thickness; Forming a spacer having an etch selectivity relative to the semiconductor substrate along the periphery of the photoresist pattern; Forming a trench having a predetermined depth in the semiconductor substrate by applying the photoresist pattern and the spacer as an etching mask; And filling the trench with an insulating material. 제1항에 있어서, 상기 산화막의 두께는 100Å∼500Å 정도인 것을 특징으로 하는 트렌치 소자분리방법.The method of claim 1, wherein the thickness of the oxide layer is about 100 Å to 500 Å. 제2항에 있어서, 상기 스페이서는 고온산화막(HTO)이나 질화막으로 이루어진 것을 특징으로 하는 트렌치 소자분리방법.The trench isolation method according to claim 2, wherein the spacer is made of a high-temperature oxide (HTO) film or a nitride film. 제3항에 있어서, 상기 트렌치는, 그 하부 사이즈가 그 상부 오프닝 사이즈보다 작은 슬로프를 갖도록 식각되는 것을 특징으로 하는 트렌치 소자분리방법.4. The method of claim 3, wherein the trench is etched so that its bottom size has a smaller slope than its top opening size. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960016960A 1996-05-20 1996-05-20 Trench element isolation method of semiconductor element KR0183859B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960016960A KR0183859B1 (en) 1996-05-20 1996-05-20 Trench element isolation method of semiconductor element

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Application Number Priority Date Filing Date Title
KR1019960016960A KR0183859B1 (en) 1996-05-20 1996-05-20 Trench element isolation method of semiconductor element

Publications (2)

Publication Number Publication Date
KR970077773A true KR970077773A (en) 1997-12-12
KR0183859B1 KR0183859B1 (en) 1999-04-15

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KR0183859B1 (en) 1999-04-15

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