KR100451494B1 - Device Separating Method of Semiconductor Device - Google Patents
Device Separating Method of Semiconductor Device Download PDFInfo
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- KR100451494B1 KR100451494B1 KR10-1998-0045777A KR19980045777A KR100451494B1 KR 100451494 B1 KR100451494 B1 KR 100451494B1 KR 19980045777 A KR19980045777 A KR 19980045777A KR 100451494 B1 KR100451494 B1 KR 100451494B1
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000002955 isolation Methods 0.000 claims abstract description 32
- 150000004767 nitrides Chemical class 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000001312 dry etching Methods 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims description 28
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 2
- 239000007789 gas Substances 0.000 description 32
- 238000002156 mixing Methods 0.000 description 6
- 238000011109 contamination Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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Abstract
본 발명은 소자분리막의 상부 에지 부분이 손실되는 것을 방지하여 게이트 산화막의 특성을 향상시킴과 더불어 누설전류를 방지할 수 있는 반도체 소자의 소자분리막 형성방법을 개시한다. 개시된 본 발명에 따른 반도체 소자의 소자분리막은 다음과 같이 형성된다. 먼저, 실리콘 기판 상에 패드 산화막 및 질화막을 순차적으로 형성하고, 질화막 및 패드 산화막을 NF3/CF4/Ar 또는 NF3/CHF3/CF4/Ar의 혼합가스를 이용한 1차 건식식각으로 과도식각하여 기판 비활성영역을 노출시킴과 동시에 상기 노출된 기판 비활성 영역의 표면에 양측벽이 라운딩된 경사를 갖는 요홈을 형성한다. 그런다음, 요홈을 구비한 기판을 NF3/CF4/Ar 또는 NF3/CHF3/CF4/Ar의 혼합가스를 이용한 2차 건식식각으로 식각하여 저부 및 상부 에지가 라운딩된 경사를 갖는 트렌치를 형성한다. 이어서, 기판 전면에 매립 능력이 우수한 산화막을 형성하여 트렌치가 매립되도록 한 후, 산화막을 질화막의 표면이 노출될 때까지 전면 식각한다. 그리고나서, 질화막 및 패드 산화막을 차례로 제거하여 소자분리막의 형성을 완성한다.The present invention discloses a method of forming a device isolation film of a semiconductor device capable of preventing the upper edge portion of the device isolation film from being lost, thereby improving the characteristics of the gate oxide film and preventing leakage current. A device isolation film of a semiconductor device according to the disclosed invention is formed as follows. First, a pad oxide film and a nitride film are sequentially formed on a silicon substrate, and the nitride film and the pad oxide film are overetched by primary dry etching using a mixed gas of NF 3 / CF 4 / Ar or NF 3 / CHF 3 / CF 4 / Ar. And at the same time, a groove having a slope with rounded sidewalls is formed on the surface of the exposed substrate inactive region. Subsequently, the recessed substrate is etched by secondary dry etching using a mixed gas of NF 3 / CF 4 / Ar or NF 3 / CHF 3 / CF 4 / Ar to form a trench having rounded bottom and top edges. Subsequently, an oxide film having excellent embedding ability is formed on the entire surface of the substrate so that the trench is buried, and the oxide film is etched entirely until the surface of the nitride film is exposed. Then, the nitride film and the pad oxide film are sequentially removed to form the device isolation film.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히, 트렌치형 소자분리막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a trench type isolation layer.
소자 분리(ISOLATION) 기술이란, 집적 소자를 구성하는 개별 소자를 전기적 및 구조적으로 서로 분리시켜, 각 소자가 인접한 소자의 간섭을 받지 않고 주어진기능을 독자적으로 수행할 수 있도록 하는데 필요한 기능을 집적 소자 제조시에 부여하는 기술이다.ISOLATION technology is an integrated device fabrication process that separates the individual devices that make up an integrated device from each other, both electrically and structurally, so that each device can perform its own function independently without interference from adjacent devices. This is a skill given to the city.
이러한 소자 분리 방법으로는 일반적으로 로코스(LOCOS : LOCal Oxidation of Silicon) 방법이 널리 공지되어 있다. 이러한 로코스 방법은 실리콘 기판상에 패드 산화막 및 질화막을 형성한 후에 필드 영역에 해당하는 실리콘 기판 부분이 노출되도록 상기 패드 산화막 및 질화막을 식각하고, 이어서, 열산화 공정을 실시하여 상기 필드 영역에 필드 산화막이라 일컬어지는 소자분리막을 형성하는 방법이다.As a device isolation method, a LOCOS (LOCal Oxidation of Silicon) method is generally known. In the LOCOS method, after the pad oxide film and the nitride film are formed on a silicon substrate, the pad oxide film and the nitride film are etched to expose a portion of the silicon substrate corresponding to the field region, and then a thermal oxidation process is performed to fill the field region. It is a method of forming an element isolation film called an oxide film.
그러나, 상기와 같은 로코스 방법은 필드 산화막의 형성시에 측면 산화에 의한 버즈-빅(bird′s-beak) 현상이 발생되는 것으로 인하여 반도체 소자의 활성 영역을 감소시키게 됨으로써, 고집적 반도체 소자의 제조에는 적용시킬 수 없는 문제점이 있었다.However, the LOCOS method as described above reduces the active area of the semiconductor device due to the occurrence of a bird's-beak phenomenon due to lateral oxidation when the field oxide film is formed, thereby manufacturing a highly integrated semiconductor device. There was a problem that could not be applied.
따라서, 근래에는 실리콘 기판의 소정 두께를 식각하여 트렌치를 형성한 후, 그 내부에 산화막이 매립되어 형성되는 트렌치형 소자분리막이 대두되고 있으며, 이러한 트렌치형 소자분리막은 그 폭이 매우 좁기 때문에 반도체 장치의 고집적화 및 고속화 경향에 매우 용이하게 대응시킬 수 있다.Therefore, in recent years, trenches are formed by etching a predetermined thickness of a silicon substrate to form trenches, and an oxide film is embedded therein. Since the trench type isolation layers have a very narrow width, semiconductor devices are formed. It is very easy to cope with the trend of high integration and high speed.
특히, 얕은 트렌치형 소자분리(Shallow Trench Isolation; 이하, STI) 기술은 초고집적 소자에 효과적으로 적용된다.In particular, shallow trench isolation (STI) technology is effectively applied to ultra-high density devices.
도 1a 내지 도 1d는 상기한 STI 기술을 이용한 종래의 반도체 소자의 소자 분리 방법을 설명하기 위한 단면도이다.1A to 1D are cross-sectional views illustrating a device isolation method of a conventional semiconductor device using the above-described STI technology.
우선, 도 1a에 도시된 바와 같이, 실리콘 기판(11) 상에 패드 산화막(12) 및 질화막(13)을 순차적으로 형성한다. 여기서, 패드 산화막(12)은 질화막(13)으로 인한 스트레스를 완화시킨다. 그런 다음, 질화막(13) 및 패드 산화막(12)을 기판(11)의 비활성영역이 노출되도록 패터닝한다. 패터닝된 질화막(13) 및 패드 산화막(12)을 식각 마스크로 하여 노출된 기판(11)을 소정 깊이로 식각하여 얕은 깊이의 트렌치(14)를 형성한다. 이때, 트렌치(14)의 저부 에지 부분은 이후에 증착되는 산화막이 트렌치(14) 내부에 완전히 매립될 수 있도록 소정의 경사를 갖도록 한다.First, as shown in FIG. 1A, the pad oxide film 12 and the nitride film 13 are sequentially formed on the silicon substrate 11. Here, the pad oxide film 12 relieves stress due to the nitride film 13. Then, the nitride film 13 and the pad oxide film 12 are patterned so that the inactive region of the substrate 11 is exposed. Using the patterned nitride film 13 and the pad oxide film 12 as an etching mask, the exposed substrate 11 is etched to a predetermined depth to form a trench 14 having a shallow depth. At this time, the bottom edge portion of the trench 14 has a predetermined inclination so that the oxide film deposited thereafter may be completely embedded in the trench 14.
그런 다음, 도 1b에 도시된 바와 같이, 트렌치(14)에 매립되도록 질화막(13) 상에 매립(gap filling) 능력이 우수한 산화막(15)을 증착하고, 화학적 기계적 연마(Chemical Mechnical Polishing; 이하, CMP)로 질화막(13)의 표면이 노출될 때까지 상기 산화막(15)을 전면 식각한다.Then, as illustrated in FIG. 1B, an oxide film 15 having excellent gap filling ability is deposited on the nitride film 13 so as to be embedded in the trench 14, and chemical mechanical polishing (hereinafter, The oxide film 15 is completely etched until the surface of the nitride film 13 is exposed by CMP.
다음으로, 도 1c에 도시된 바와 같이, 기판(11)과의 단차(A)가 0 내지 500Å정도가 되도록, HF 또는 BOE(Buffered Oxide Etchnat) 용액을 이용하여 산화막(15)을 식각한 후, H3PO4용액으로 질화막(13)을 제거한다.Next, as shown in FIG. 1C, after the oxide film 15 is etched using HF or BOE (Buffered Oxide Etchnat) solution so that the step A with the substrate 11 is about 0 to 500 kV, The nitride film 13 is removed with a H 3 PO 4 solution.
그리고나서, 도 1d에 도시된 바와 같이, 습식 식각으로 패드 산화막(12)을 제거하여, 소자분리막(15a)을 완성한다.Then, as shown in FIG. 1D, the pad oxide layer 12 is removed by wet etching to complete the device isolation layer 15a.
그러나, 도 1d에 도시된 바와 같이, 패드 산화막(12) 제거를 위한 습식식각시, 패드산화막(12)과 접하는 소자분리막(15a)의 에지가 소정 부분 손실된다.However, as shown in FIG. 1D, during wet etching for removing the pad oxide film 12, a predetermined portion of the edge of the device isolation film 15a in contact with the pad oxide film 12 is lost.
또한, 이후 진행되는 이온주입 공정시 스크린 산화막의 형성 및 제거에서, 소자분리막(15a)의 손실은 더욱더 심해진다. 이러한, 소자분리막(15a)의 손실은 게이트 산화막의 특성을 저하시키고 누설전류를 유발시킨다.In addition, in the formation and removal of the screen oxide film during the ion implantation process, the loss of the device isolation film 15a becomes more severe. This loss of the device isolation film 15a degrades the characteristics of the gate oxide film and causes leakage current.
게다가, 게이트 형성을 위한 식각공정시 손실된 부분에 화학물질 및 게이트 물질등이 잔재하여, 결국 소자의 전기적 특성 및 신뢰성을 저하시킨다.In addition, chemicals and gate materials remain in portions that are lost during the etching process for gate formation, resulting in deterioration of electrical characteristics and reliability of the device.
따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위해 안출된 것으로서, 소자분리막의 에지 부분의 손실을 방지하여 게이트 산화막의 특성을 향상시키고, 누설전류를 방지할 수 있는 반도체 소자의 소자분리막 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and prevents the loss of the edge portion of the device isolation film, thereby improving the characteristics of the gate oxide film and preventing the leakage current of the device. The purpose is to provide.
도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자의 소자분리막 형성방법을 설명하기 위한 단면도.1A to 1D are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device according to the prior art.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 소자분리막 형성방법을 설명하기 위한 단면도.2A to 2D are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device in accordance with an embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
31 : 반도체 기판 32 : 패드 산화막31 semiconductor substrate 32 pad oxide film
33 : 질화막 34 : 마스크 패턴33: nitride film 34: mask pattern
35 : 요홈 36 : 트렌치35: groove 36: trench
37 : 산화막 37a : 소자분리막37 oxide film 37a device isolation film
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 소자분리막 형성방법은, 비활성 영역을 구비한 실리콘 기판 상에 패드산화막과 질화막을 순차적으로 형성하는 단계; 상기 질화막과 패드산화막을 NF3/CF4/Ar 또는 NF3/CHF3/CF4/Ar의 혼합가스를 이용한 1차 건식식각으로 과도식각하여 기판 비활성영역을 노출시킴과 동시에 상기 노출된 기판 비활성 영역의 표면에 양측벽이 라운딩된 경사를 갖는 요홈을 형성하는 단계; 및 상기 요홈을 구비한 기판을 NF3/CF4/Ar 또는 NF3/CHF3/CF4/Ar의 혼합가스를 이용한 2차 건식식각으로 식각하여 저부 및 상부 에지가 라운딩된 경사를 갖는 트렌치를 형성하는 단계를 포함하는 것을 특징으로 한다.A device isolation film forming method of a semiconductor device according to the present invention for achieving the above object comprises the steps of sequentially forming a pad oxide film and a nitride film on a silicon substrate having an inactive region; The nitride film and the pad oxide film are excessively etched by primary dry etching using a mixed gas of NF 3 / CF 4 / Ar or NF 3 / CHF 3 / CF 4 / Ar to expose the substrate inactive region, and at both sides of the exposed surface of the substrate inactive region. Forming a recess having a walled inclination; And etching the substrate having the recess with secondary dry etching using a mixed gas of NF 3 / CF 4 / Ar or NF 3 / CHF 3 / CF 4 / Ar to form a trench having rounded bottom and top edges. Characterized in that.
또한, 본 발명에 따른 반도체 소자의 소자분리막 형성방법은, 상기 트렌치를형성하는 단계 이후에, 상기 트렌치가 매립되도록 상기 기판 전면에 매립 능력이 우수한 산화막을 형성하는 단계; 상기 산화막을 상기 질화막의 표면이 노출될때까지 전면 식각하는 단계; 상기 산화막을 상기 기판과 소정의 단차를 갖도록 식각하는 단계; 상기 질화막을 제거하는 단계; 및 상기 패드 산화막을 제거하는 단계를 더 포함한다.In addition, the method of forming a device isolation film of a semiconductor device according to the present invention, after the step of forming the trench, the step of forming an oxide film having excellent embedding capability on the entire surface of the substrate to fill the trench; Etching the oxide film entirely until the surface of the nitride film is exposed; Etching the oxide film to have a predetermined step with the substrate; Removing the nitride film; And removing the pad oxide layer.
(실시예)(Example)
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 소자분리막 형성방법을 설명하기 위한 단면도이다.2A through 2E are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device according to an embodiment of the present invention.
도 2a를 참조하면, 반도체 기판(31) 상에 약 100 내지 200Å의 두께로 패드 산화막(12)을 형성하고, 상기 패드 산화막(12) 상에 약 500 내지 3,000Å의 두께로 질화막(13)을 형성한다. 여기서, 패드 산화막(12)은 질화막(12)으로 인한 스트레스를 완화시킨다. 그런 다음, 질화막(33) 상에 포토리소그라피 공정을 통해 마스크 패턴(34)을 형성하고, 상기 마스크 패턴(34)을 식각 마스크로하는 제1식각 공정을 통해 질화막(33) 및 패드 산화막(32)의 소정 부분을 과도식각하여 기판(31)의 비활성영역을 노출시킴과 동시에 노출된 기판(31)에 양 측벽이 라운딩된 경사를 갖는 요홈(35)을 형성한다.Referring to FIG. 2A, a pad oxide film 12 is formed on the semiconductor substrate 31 with a thickness of about 100 to 200 mW, and the nitride film 13 is formed on the pad oxide film 12 to a thickness of about 500 to 3,000 mW. Form. Here, the pad oxide film 12 relieves stress due to the nitride film 12. Then, the mask pattern 34 is formed on the nitride film 33 through a photolithography process, and the nitride film 33 and the pad oxide film 32 are formed through a first etching process using the mask pattern 34 as an etch mask. A portion of the substrate is overetched to expose the inactive region of the substrate 31, and at the same time, a groove 35 having an inclined rounded sidewall is formed in the exposed substrate 31.
여기서, 제1식각 공정은 건식 식각으로 진행하며, 아울러, RIE(Reactive Ion Etching) 또는 ME-RIE 장비를 이용하여 진행하고, 이때, 식각 가스로는 NF3/CF4/Ar의 혼합가스, 또는, NF3/CHF3/CF4/Ar의 혼합가스를 사용한다.Here, the first etching process is performed by dry etching, and further, using a reactive ion etching (RIE) or ME-RIE equipment, wherein the etching gas is a mixed gas of NF 3 / CF 4 / Ar, or, A mixed gas of NF 3 / CHF 3 / CF 4 / Ar is used.
도 2b를 참조하면, 요홈(35)이 형성된 기판(31)에 대한 제2식각 공정을 통해 소정 깊이만큼 식각하여 저부 및 상부 에지가 라운딩된 경사를 갖는 트렌치(36)를 형성한다. 여기서, 제2식각 공정은 건식 식각으로 진행하며, 식각 가스로는 제1식각 공정과 마찬가지로, NF3/CF4/Ar의 혼합가스, 또는, NF3/CHF3/CF4/Ar의 혼합가스를 사용한다. 그런 다음, 공지된 방법으로 마스크 패턴(34)을 제거한다. 이때, 마스크 패턴(34)은 트렌치(36)의 형성전에 제거될 수 있다.Referring to FIG. 2B, a trench 36 having a slope having rounded bottom and upper edges is formed by etching a predetermined depth through a second etching process on the substrate 31 on which the recess 35 is formed. The second etching process may be performed by dry etching, and as an etching gas, a mixed gas of NF 3 / CF 4 / Ar or a mixed gas of NF 3 / CHF 3 / CF 4 / Ar may be used as the etching gas. use. The mask pattern 34 is then removed in a known manner. In this case, the mask pattern 34 may be removed before the formation of the trench 36.
도 2c를 참조하면, 트렌치(36)가 매립되도록 질화막(33) 상에 매립 능력이 우수한 산화막(37), 예컨데, HDP 산화막, O3-TEOS 산화막, LP-TEOS 산화막, PE-TEOS 산화막, BPSG막, 또는, SOG막 등으로 이루어진 그룹으로부터 선택되는 하나의 막을 형성한다. 그런 다음, 질화막(33)을 식각정지막으로 하여 CMP로 질화막(33)의 표면이 노출될 때까지 산화막(37)을 전면식각한다. 여기서, CMP 대신에 CHF3, CF4, C2F6, C3F8, C4F8의 프레온가스 계열로 이루어진 그룹으로부터 선택되는 하나의 가스를 이용하여 건식식각으로 산화막(37)을 식각할 수 있다. 다음으로, 기판(11)과의 단차(A)가 100 내지 500Å 정도가 되도록 HF 나 BOE 용액을 이용하여 산화막(37)을 재차 식각한 후, H3PO4용액으로 질화막(33)을 제거한다.Referring to FIG. 2C, an oxide film 37 having excellent embedding capability on the nitride film 33 such that the trench 36 is embedded, for example, an HDP oxide film, an O 3 -TEOS oxide film, an LP-TEOS oxide film, a PE-TEOS oxide film, and a BPSG One film selected from the group consisting of a film or an SOG film or the like is formed. Then, using the nitride film 33 as an etch stop film, the oxide film 37 is completely etched until the surface of the nitride film 33 is exposed by CMP. Here, instead of CMP, the oxide film 37 is etched by dry etching using one gas selected from the group consisting of a group of freon gases of CHF 3 , CF 4 , C 2 F 6 , C 3 F 8 , and C 4 F 8 . can do. Next, the oxide film 37 is etched again using HF or BOE solution so that the step A with the substrate 11 is about 100 to 500 kV, and then the nitride film 33 is removed with the H 3 PO 4 solution. .
그리고 나서, 도 2d에 도시된 바와 같이, 습식 식각으로 패드 산화막(32)을 제거하여 소자분리막(37a)을 완성한다. 이때, 소자분리막(37a)은 그의 상부 부분이라운딩되어 있는 것에 기인하여 패드 산화막(32)의 제거시에 손실이 방지된다. 또한, 이후 진행될 이온주입 공정에서 스크린 산화막의 형성 및 제거시에도 소자분리막(37a)의 손실이 효과적으로 방지된다.Then, as shown in FIG. 2D, the pad oxide layer 32 is removed by wet etching to complete the device isolation layer 37a. At this time, the element isolation film 37a is prevented from being lost when the pad oxide film 32 is removed due to its upper portion being rounded. In addition, the loss of the device isolation film 37a is effectively prevented even when the screen oxide film is formed and removed in the ion implantation process to be performed later.
한편, 질화막 및 실리콘 기판에 대한 건식 식각시에는 일반적으로 CHF3/CF4가스를 사용한다. 그런데, 이러한 가스를 사용하여 식각 공정을 진행할 경우에는 식각 공정이 불안정함은 물론 상기한 식각 가스에 의해 챔버의 오염이 발생된다.Meanwhile, CHF 3 / CF 4 gas is generally used for dry etching of the nitride film and the silicon substrate. However, when the etching process is performed using such a gas, the etching process may be unstable and contamination of the chamber may be generated by the etching gas.
그러나, 본 발명의 실시예에서는 식각 가스로서 NF3/CF4/Ar의 혼합가스, 또는, NF3/CHF3/CF4/Ar의 혼합가스를 사용하는데, 이때, 식각 가스인 CF4가스와 세정 가스인 NF3가스의 혼합비율을 적절하게 조절하면, 안정된 식각 공정을 수행할 수 있음은 물론 챔버의 오염을 방지할 수 있다.However, in the embodiment of the present invention is used as the etching gas NF 3 / CF 4 / mixed gas of Ar, or, NF 3 / CHF 3 / CF 4 / Ar to a mixed gas of this time, the etching gas of CF 4 gas and By properly adjusting the mixing ratio of the NF 3 gas, which is a cleaning gas, it is possible to perform a stable etching process and to prevent contamination of the chamber.
즉, 식각 가스인 CF4가스의 혼합량을 증가시킬 경우에는 트렌치의 에지가 수직으로 되고, 반대로, CF4가스의 혼합량을 감소시킬 경우에는 트렌치의 에지가 경사지게 되는 현상을 이용함으로써, 트렌치의 저부 및 상부의 라운딩되는 정도 및 전체적인 트렌치 내벽의 경사 정도를 제어할 수 있으며, 특히, 상기한 CF4가스와 NF3가스의 혼합비율을 변경하면서 3회 이상의 건식 식각을 수행할 경우에는 트렌치 내벽의 경사 정도를 더욱 완만하게 할 수 있어서, 산화막의 매립 특성은 물론 소자분리막의 손실 방지를 효과적으로 이룰 수 있다.In other words, when the mixing amount of CF 4 gas, which is an etching gas, is increased, the edge of the trench becomes vertical. On the contrary, when the mixing amount of CF 4 gas is decreased, the edge of the trench is inclined. The rounding degree of the upper part and the degree of inclination of the entire trench inner wall can be controlled. In particular, when the dry etching is performed three or more times while changing the mixing ratio of the CF 4 gas and the NF 3 gas, the degree of inclination of the inner wall of the trench is controlled. It can be made more gentle, it is possible to effectively prevent the loss of the isolation layer as well as the buried characteristics of the oxide film.
또한, 세정 가스인 NF3가스의 혼합비율을 증가시킴으로써, 챔버내의 오염을 방지할 수 있게 된다.In addition, by increasing the mixing ratio of the NF 3 gas, which is a cleaning gas, contamination in the chamber can be prevented.
상기한 본 발명에 의하면, 소자분리막의 상부 에지 부분이 라운딩되도록 함으로써, 패드 산화막의 제거시에 상기 소자분리막의 상부 에지 부분이 손실되는 것을 방지할 수 있다. 이에 따라, 소자분리막의 손실로 인한 게이트 산화막의 특성 저하 및 누설전류 등을 방지할 수 있게 된다. 또한, 게이트 형성을 위한 식각공정시 화학물질 및 게이트 물질등이 잔재하지 않으므로, 결국 소자의 전기적 특성 및 신뢰성이 향상된다.According to the present invention described above, by rounding the upper edge portion of the device isolation film, it is possible to prevent the upper edge portion of the device isolation film from being lost when the pad oxide film is removed. Accordingly, it is possible to prevent the deterioration of the characteristics of the gate oxide film and the leakage current due to the loss of the device isolation film. In addition, since chemicals and gate materials do not remain during the etching process for forming the gate, the electrical characteristics and reliability of the device are improved.
게다가, 식각 가스인 CF4가스와 세정 가스인 NF3가스의 혼합비율을 적절하게 조절함으로써 챔버의 오염을 방지할 수 있게 되는 바, 장비 가동률을 향상시킬 수 있다.In addition, it is possible to prevent contamination of the chamber by appropriately adjusting the mixing ratio of the CF 4 gas, which is the etching gas, and the NF 3 gas, which is the cleaning gas, thereby improving the equipment operation rate.
한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
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| KR100849080B1 (en) * | 2002-06-28 | 2008-07-30 | 매그나칩 반도체 유한회사 | Method for forming isolation film in semiconductor device |
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| JPH08274157A (en) * | 1995-03-31 | 1996-10-18 | Toyota Central Res & Dev Lab Inc | Semiconductor device and its manufacture |
| KR970003795A (en) * | 1995-06-23 | 1997-01-29 | 김광호 | Device Separation Method Using Isotropic and Anisotropic Etching |
| KR970018374A (en) * | 1995-09-21 | 1997-04-30 | 김광호 | Device Separation Method of Semiconductor Device |
| KR970018357A (en) * | 1995-09-07 | 1997-04-30 | 김광호 | Trench Formation Method of Semiconductor Device |
| JPH104136A (en) * | 1996-04-15 | 1998-01-06 | Samsung Electron Co Ltd | Method for forming element isolating film of semiconductor device |
| KR0183854B1 (en) * | 1996-05-15 | 1999-04-15 | 김광호 | Trench element isolation method of semiconductor element |
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| JPH08274157A (en) * | 1995-03-31 | 1996-10-18 | Toyota Central Res & Dev Lab Inc | Semiconductor device and its manufacture |
| KR970003795A (en) * | 1995-06-23 | 1997-01-29 | 김광호 | Device Separation Method Using Isotropic and Anisotropic Etching |
| KR970018357A (en) * | 1995-09-07 | 1997-04-30 | 김광호 | Trench Formation Method of Semiconductor Device |
| KR970018374A (en) * | 1995-09-21 | 1997-04-30 | 김광호 | Device Separation Method of Semiconductor Device |
| JPH104136A (en) * | 1996-04-15 | 1998-01-06 | Samsung Electron Co Ltd | Method for forming element isolating film of semiconductor device |
| KR0183854B1 (en) * | 1996-05-15 | 1999-04-15 | 김광호 | Trench element isolation method of semiconductor element |
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