KR970072310A - 집적 회로 절연체 및 방법 - Google Patents
집적 회로 절연체 및 방법 Download PDFInfo
- Publication number
- KR970072310A KR970072310A KR1019970016238A KR19970016238A KR970072310A KR 970072310 A KR970072310 A KR 970072310A KR 1019970016238 A KR1019970016238 A KR 1019970016238A KR 19970016238 A KR19970016238 A KR 19970016238A KR 970072310 A KR970072310 A KR 970072310A
- Authority
- KR
- South Korea
- Prior art keywords
- integrated circuit
- dielectric constant
- dielectric material
- dielectric
- interlevel
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 메탈 레벨내의 갭 충전(140)을 위한 하나와 메탈 레벨들 사이를 위한 다른 하나(150)인 두개의 다른 저 유전 상수 절연체들을 갖는 인터메탈 레벨 유전체에 관한 것이다.
본 발명의 양호한 실시예는 갭 충전 저 유전 상수 절연체로서의 HSQ(140) 및 메탈 레벨 사이(between) 저 유전 상수 절연체로서의 불소첨가 실리콘 산화물(150)을 포함한다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1a-e도는 제1양호한 실시예 및 방법의 단계들을 도시한 횡단면도.
Claims (3)
- 집적 회로 인터레벨 절연 구조에 있어서, (a) 제1도전체에 인접하고 최대 약 3.7의 유전 상수를 갖는 제1유전 재료로 이루어진 제1절연체 영역, 및 (b) 상기 제1절연체 영역과 상기 제1도전체 위에 및 제2도전체 아래에 위치하고, 상기 제1유전 재료와 다른 제2유전 재료로 이루어지며 약 3.7 미만의 유전 상수를 갖는 제2절연체 영역을 포함하는 것을 특징으로 하는 집적 회로 인터레벨 절연 구조.
- 제1항에 있어서, 상기 제1유전 재료는 상기 제2유전 재료의 유전 상수보다 작은 유전 상수를 갖는 것을 특징으로 하는 집적 회로 인터레벨 절연 구조.
- 제1항에 있어서, 상기 제1영역 및 상기 제2영역 사이에 세퍼레이(separator)층을 더 포함하는 것을 특징으로 하는 집적 회로 인터레벨 절연 구조.※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US1640396P | 1996-04-29 | 1996-04-29 | |
US60/016,403 | 1996-04-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970072310A true KR970072310A (ko) | 1997-11-07 |
KR100518988B1 KR100518988B1 (ko) | 2005-12-01 |
Family
ID=21776953
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019970016238A KR100518988B1 (ko) | 1996-04-29 | 1997-04-29 | 집적회로절연체및그제조방법 |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0805491A3 (ko) |
JP (1) | JPH1041382A (ko) |
KR (1) | KR100518988B1 (ko) |
TW (1) | TW391048B (ko) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3159093B2 (ja) * | 1996-12-25 | 2001-04-23 | 日本電気株式会社 | 半導体装置およびその製造方法 |
JPH10189723A (ja) * | 1996-12-25 | 1998-07-21 | Nec Corp | 半導体装置およびその製造方法 |
US6770975B2 (en) * | 1999-06-09 | 2004-08-03 | Alliedsignal Inc. | Integrated circuits with multiple low dielectric-constant inter-metal dielectrics |
US6391795B1 (en) * | 1999-10-22 | 2002-05-21 | Lsi Logic Corporation | Low k dielectric composite layer for intergrated circuit structure which provides void-free low k dielectric material between metal lines while mitigating via poisoning |
KR100326814B1 (ko) * | 1999-12-30 | 2002-03-04 | 박종섭 | 반도체 소자의 금속배선간 층간 절연막 형성방법 |
JP4752108B2 (ja) | 2000-12-08 | 2011-08-17 | ソニー株式会社 | 半導体装置およびその製造方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5565384A (en) * | 1994-04-28 | 1996-10-15 | Texas Instruments Inc | Self-aligned via using low permittivity dielectric |
US5476817A (en) * | 1994-05-31 | 1995-12-19 | Texas Instruments Incorporated | Method of making reliable metal leads in high speed LSI semiconductors using both dummy leads and thermoconductive layers |
JPH08162528A (ja) * | 1994-10-03 | 1996-06-21 | Sony Corp | 半導体装置の層間絶縁膜構造 |
-
1997
- 1997-04-28 JP JP9111615A patent/JPH1041382A/ja active Pending
- 1997-04-28 TW TW086105508A patent/TW391048B/zh not_active IP Right Cessation
- 1997-04-29 EP EP97107086A patent/EP0805491A3/en not_active Withdrawn
- 1997-04-29 KR KR1019970016238A patent/KR100518988B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
JPH1041382A (ja) | 1998-02-13 |
EP0805491A3 (en) | 1997-11-12 |
KR100518988B1 (ko) | 2005-12-01 |
TW391048B (en) | 2000-05-21 |
EP0805491A2 (en) | 1997-11-05 |
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