KR970068667A - MPEG data receiving device - Google Patents
MPEG data receiving device Download PDFInfo
- Publication number
- KR970068667A KR970068667A KR1019960006354A KR19960006354A KR970068667A KR 970068667 A KR970068667 A KR 970068667A KR 1019960006354 A KR1019960006354 A KR 1019960006354A KR 19960006354 A KR19960006354 A KR 19960006354A KR 970068667 A KR970068667 A KR 970068667A
- Authority
- KR
- South Korea
- Prior art keywords
- data
- bit
- out memory
- mpeg
- parallel
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/434—Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
- H04N21/4305—Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Compression Or Coding Systems Of Tv Signals (AREA)
- Communication Control (AREA)
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. Technical field to which the invention described in the claims belongs
엠펙데이타 수신장치에 관한 것이다.And an MPEG data receiving apparatus.
2. 발명이 해결하려고 하는 기술적 과제2. Technical Challenges to be Solved by the Invention
망으로부터 수신되는 직렬형태의 엠펙데이타를 중앙처리장치가 실시간으로 처리할 수 있는 병렬형태의 엠펙데이타로 변환하는 장치를 구현한다.And implements an apparatus for converting serial data in a serial form received from a network into parallel data in a form that can be processed in real time by a central processing unit.
3. 발명의 해결방법의 요지3. The point of the solution of the invention
본 발명에 따른 엠펙데이타 수신장치는, 망으로부터의 엠펙스트림을 라인디코딩하여 직렬형태의 엠펙데이타를 출력하는 라인디코딩수단과, 상기 직렬형태의 엠펙데이타를 병렬형태의 데이타로 변환하는 직병렬변환수단과, 상기 직병렬변환수단에 의해 병렬형태로 변환된 데이타를 선택적으로 비트변환하여 출력하는 비트변환수단과, 상기 비트변환수단의 출력을 라이트신호에 따라 라이트하는 선입선출메모리와, 상기 엠펙스트림내에 동기바이트가 포함된 경우 상기 라이트신호를 발생시켜 상기 비트변환수단의 출력이 상기 선입선출메모리에 라이트되도록 제어하는 라이트제어수단과, 상기 선입선출메모리에 라이트되어 있는 데이타를 리드하는 중앙처리장치로 구성된다.An apparatus for receiving MPEG data according to the present invention comprises: line decoding means for line decoding a MPEG stream from a network and outputting serialized MPEG data; serial-to-parallel conversion means for converting the serialized MPEG data into parallel- A first-in-first-out memory for selectively outputting the parallel-converted data by the serial-to-parallel conversion means and outputting the bit-converted data, a first-in-first-out memory for writing the output of the bit- Write control means for generating the write signal when the synchronous byte is included and controlling the output of the bit conversion means to be written to the first-in-first-out memory, and a central processing unit for reading the data written in the first- do.
4. 발명의 중요한 용도4. Important Uses of the Invention
주문형 비디오의 엠펙데이타 수신장치.An apparatus for receiving MPEG data of video on demand.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.
제2도는 본 발명에 따른 엠펙데이타 수신장치에 대한 블럭다이아그램, 제3도는 제2도에서 직렬/병렬변환부, 선입선출메모리(FIFO), 비트변환부 및 라이트신호발생부의 연결구성을 상세하게 나타내는 도면, 제4도는 제3도에서 비트변환부에 대한 상세구성도, 제5도는 본 발명에 따른 엠펙데이타 수신장치에 대한 동작파형도, 제6도는 본 발명에 따른 동작을 설명하기 위한 도면.FIG. 2 is a block diagram of an MPEG data receiving apparatus according to the present invention, FIG. 3 is a detailed diagram of a connection configuration of a serial / parallel conversion unit, a FIFO, a bit conversion unit, FIG. 5 is a waveform diagram for an MPEG data receiving apparatus according to the present invention; FIG. 6 is a view for explaining an operation according to the present invention; FIG.
Claims (19)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960006354A KR100242309B1 (en) | 1996-03-11 | 1996-03-11 | Apparatus for receiving mpeg data |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960006354A KR100242309B1 (en) | 1996-03-11 | 1996-03-11 | Apparatus for receiving mpeg data |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970068667A true KR970068667A (en) | 1997-10-13 |
KR100242309B1 KR100242309B1 (en) | 2000-02-01 |
Family
ID=19452790
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019960006354A KR100242309B1 (en) | 1996-03-11 | 1996-03-11 | Apparatus for receiving mpeg data |
Country Status (1)
Country | Link |
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KR (1) | KR100242309B1 (en) |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6444689A (en) * | 1987-08-12 | 1989-02-17 | Toshiba Corp | Teletext receiver |
-
1996
- 1996-03-11 KR KR1019960006354A patent/KR100242309B1/en not_active IP Right Cessation
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Publication number | Publication date |
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KR100242309B1 (en) | 2000-02-01 |
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