KR970057216A

KR970057216A - Horizontal Synchronization Correction Circuit of On Screen Display

Info

Publication number: KR970057216A
Application number: KR1019950061965A
Authority: KR
Inventors: 권성섭
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-12-28
Filing date: 1995-12-28
Publication date: 1997-07-31

Abstract

본 발명은 문자 디스플레이의 동작 기준이 되는 수평동기신호의 주파수를 안정하게 해주는 온 스크린 디스플레이의 수평동기보정회로에 관한 것이다.The present invention relates to a horizontal synchronous correction circuit of an on-screen display for stabilizing the frequency of the horizontal synchronous signal which is an operation reference of a character display.

수직동기신호(Vsync)를 수신하여 상기의 수직동기신호(Vsync)의 하강에지에서 하이논리값을 가지며 하이논리값일 때 아날로그 위상동기루프회로(3)가 동작되는 위상동기 인에이블신호(PLLE)를 출력하는 제1플립플롭(DFF1), 상기의 위상동기 인에이블신호(PLLE)가 하이논리값을 가질 때 수평동기신호(Hsync)에 동기되어 1씩 증가되고 상기의 위상동기 인에이블신호(PLLE)가 로우논리값일때 리세되는 카운터수단(11) 및 상기의 카운터수단(11)의 출력이 십진수 20일때 수직동기신호(Vsync)의 하강에지에서 상기의 제1플립플롭(DFF1)의 출력인 위상동기 인에이블신호(PLLE)를 리셋시키는 리셋부(12)로 구성된다.Receives the vertical synchronization signal (Vsync) and has a high logic value at the falling edge of the vertical synchronization signal (Vsync), and when the analog phase synchronization loop circuit (3) is operated when the high logic value phase synchronization enable signal (PLLE) When the outputted first flip-flop DFF1 and the phase synchronization enable signal PLLE have a high logic value, they are incremented by 1 in synchronization with the horizontal synchronization signal Hsync and the phase synchronization enable signal PLLE is generated. Is the output of the first flip-flop DFF1 at the falling edge of the vertical synchronization signal Vsync when the output of the counter means 11 and the counter means 11 is 20 decimal. The reset unit 12 resets the enable signal PLLE.

Description

Horizontal synchronization correction circuit on screen display.

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 온 스크린 디스플레이의 수평동기보정회로.2 is a horizontal synchronization correction circuit for an on-screen display of the present invention.

제3도는 제2도의 타이밍도이다.3 is a timing diagram of FIG.

Claims

A synchronous separation circuit for receiving a composite video signal and separating and outputting a horizontal synchronous signal, and a horizontal synchronous signal with little jitter by suppressing the horizontal synchronous signal having jitter generated when the electric field of the composite video signal is smaller than the electric field of the reference value. An on-screen display for receiving a horizontal synchronization signal with little jitter and displaying a character in a video signal, the analog phase synchronization loop circuit outputting a signal, wherein the vertical synchronization signal is received at a falling edge of the vertical synchronization signal. A first flip-flop having a logic value and outputting a phase synchronous enable signal at which the analog phase synchronous loop circuit is operated when the logic is high, and a horizontal synchronous signal when the phase synchronous enable signal has a high logic value; Counter means synchronized with each other and reset when the phase synchronization enable signal is a low logic value; And a reset unit for resetting the phase synchronization enable signal, which is the output of the first flip-flop, at the falling edge of the vertical synchronization signal when the output of the counter means is 20 in hexadecimal. Correction circuit.

2. The apparatus of claim 1, wherein the reset unit comprises: logical multiplication means for detecting when the output of the counter means is a decimal number 20 and outputting a high logic value; And a second flip-flop for receiving the vertical synchronizing signal and outputting the output of the logical multiplication means at the falling edge of the vertical synchronizing signal.

※ Note: The disclosure is based on the initial application.