KR970004640A - Sync signal processing circuit of LCD projector - Google Patents

Sync signal processing circuit of LCD projector Download PDF

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Publication number
KR970004640A
KR970004640A KR1019950018125A KR19950018125A KR970004640A KR 970004640 A KR970004640 A KR 970004640A KR 1019950018125 A KR1019950018125 A KR 1019950018125A KR 19950018125 A KR19950018125 A KR 19950018125A KR 970004640 A KR970004640 A KR 970004640A
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KR
South Korea
Prior art keywords
sync
synchronization
signal
vertical
horizontal
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KR1019950018125A
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Korean (ko)
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KR0144885B1 (en
Inventor
김익송
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김광호
삼성전자 주식회사
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Priority to KR1019950018125A priority Critical patent/KR0144885B1/en
Publication of KR970004640A publication Critical patent/KR970004640A/en
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Publication of KR0144885B1 publication Critical patent/KR0144885B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/08—Separation of synchronising signals from picture signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/38—Starting, stopping or resetting the counter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/12—Picture reproducers
    • H04N9/31—Projection devices for colour picture display, e.g. using electronic spatial light modulators [ESLM]

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)
  • Projection Apparatus (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Transforming Electric Information Into Light Information (AREA)

Abstract

본 발명은 액정 프로젝터의 동기 신호 처리 회로에 관한 것으로, 특히 액정 프로젝터의 동기 관련 계통도(PLL)가 다단으로 구성되어 있어 시스템이 복밥한 경우 입력 동기 신호를 정상적인 경우와 비정상적인 경우로 판단하여 선택적으로 동기신호를 달리 하도록 구성한 회로에 관한 것이며, 입력되는 복합 동기 신호에서 동기 신호의 유무를 판별하는 동기 신호판별 회로부, 동기 신호 판별 회로부에서 동기 신호를 검출하였을 경우 상기 동기 분리기에서 출력되는 수평 동기 및 수직 동기를 선택하고, 동기 신호를 검출하지 못하였을 경우 상기 위상 보정된 수평 동기를 선택하고 수직 동기는 접지 시키는 동기 절환부를 포함하는 것을 특징으로 하며, 입력 신호의 유무에 따라 동기 신호를 차별화 함으로 해서, 정상적인 입력인 경우 선명한 화질을 얻을 수 있으며, 입력 동기 신호가 없는 경우에도 PLL이 안정화 되어 OSD(On Screen Display)를 제대로 볼 수 있는 잇점이 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization signal processing circuit of a liquid crystal projector. Particularly, when a system is duplicated because a synchronization related schematic diagram (PLL) of a liquid crystal projector is configured in multiple stages, the input synchronization signal is judged to be normal and abnormal and selectively synchronized. The circuit is configured to different signals, and the horizontal and vertical sync output from the sync separator when a sync signal is detected by the sync signal discrimination circuit section for discriminating the presence or absence of a sync signal in the input complex sync signal. And selecting a phase corrected horizontal sync and vertical sync when the sync signal is not detected. The sync switch may be grounded, and the sync signal may be differentiated according to the presence or absence of an input signal. If the input is clear And, the PLL is stable even in the absence of an input synchronizing signal has the advantage that you can see the OSD (On Screen Display) properly.

Description

액정 프로젝터의 동기 신호 처리 회로Sync signal processing circuit of LCD projector

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 액정 프로젝터의 동기 신호 처리 회로의 블럭도.2 is a block diagram of a synchronization signal processing circuit of the liquid crystal projector of the present invention.

Claims (2)

입력되는 복합 동기 신호를 수평 동기와 수직 동기로 분리하는 동기 분리기, 상기 수평 동기의 제어에 의해 국부 발진기의 클럭을 32분주하여 위상 제어된 수평 동기를 생성하는 32분주기, 상기 위상 제어된 수평 동기를 내부적으로 카운트하여 상기 동기 분리기에서 출력된 수직 동기의 제어에 따라 위상 보정된 수직 동기를 생성하는 수직 카운트 다운기, 상기 32분주기에서 출력된 신호를 위상 제어(PLL)하기 위한 의사 플라이 백 신호기로 구성되어 위상 보정된 수평 동기(H)와 수직 동기(V)를출력하는 동기 신호 처리부와, 상기 수평 동기와 수직 동기를 입력하여 위상 보정된 2배 수평 동기(2H)를 출력하는 배속 주사 변환부와, 상기 2H를 입력하여 액정 표시기 모뮬이 필요로 하는 클럭을 발생시키는 액정 제어부를 구비한 액정 프로젝터의 동기 신호 처리 회로에 있어서, 상기 입력되는 복합 동기 신호에서 동기 신호의 유무를 판별하는 동기 신호 판별 회로부: 상기 동기 신호 판별 회로부에서 동기 신호를 검출하였을 경우 상기 동기 분리기에서 출력되는 수평 동기 및 수직 동기를 선택하고, 도기 신호를 검출하지 못하였을 경우 상기 위상 보정된 수평 동기를 선택하고 수직 동기는 접지 시키는 동기 절환부를 포함하는 것을 특징으로 하는 액정 프로젝터의 동기 신호 처리 회로.A synchronous separator for separating the input composite synchronization signal into a horizontal sync and a vertical sync, a 32 divider which divides a clock of a local oscillator by 32 to generate a phase controlled horizontal sync by controlling the horizontal sync, and the phase controlled horizontal sync A vertical countdown that internally counts and generates a phase-corrected vertical sync according to the control of the vertical sync output from the sync separator, and a pseudo flyback signal for phase-controlling (PLL) the signal output from the 32 dividers A synchronous signal processor for outputting a phase-corrected horizontal sync (H) and a vertical sync (V), and a double-speed scan conversion for inputting the horizontal sync and vertical sync and outputting a phase-corrected double horizontal sync (2H) And a synchronization signal processing of a liquid crystal projector having a liquid crystal controller for inputting the 2H to generate a clock required by the liquid crystal display module. A synchronization signal discrimination circuit section for determining the presence or absence of a synchronization signal in the input composite synchronization signal in the furnace: when the synchronization signal detection circuit section detects a synchronization signal, selects the horizontal synchronization and vertical synchronization output from the synchronization separator, And a synchronization switch for selecting the phase corrected horizontal synchronization and grounding the vertical synchronization when no signal is detected. 제1항에 있어서, 상기 동기 절환부는 동기 신호를 검출하지 못하였을 경우 수직 동기가 접지 레벨로 되며, 상기 배속 수사 변환부와 액정 제어부에서 자체적으로 수평 동기를 기준으로 카운트 다운하여 위상이 보정된 수직 동기를 발생하는 것을 특징으로 하는 액정 프로젝터의 동기 신호 처리 회로.According to claim 1, wherein when the synchronization switching unit does not detect a synchronization signal, the vertical synchronization is a ground level, the vertical speed is corrected by counting down based on the horizontal synchronization in the double-speed investigation converter and the liquid crystal controller based on the vertical A synchronization signal processing circuit of a liquid crystal projector, characterized by generating synchronization. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950018125A 1995-06-29 1995-06-29 A sync signal processing circuit of liquid projector KR0144885B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950018125A KR0144885B1 (en) 1995-06-29 1995-06-29 A sync signal processing circuit of liquid projector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950018125A KR0144885B1 (en) 1995-06-29 1995-06-29 A sync signal processing circuit of liquid projector

Publications (2)

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KR970004640A true KR970004640A (en) 1997-01-29
KR0144885B1 KR0144885B1 (en) 1998-07-15

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100521942B1 (en) * 1998-08-22 2006-01-27 엘지전자 주식회사 OSD Character Stabilizer and Stabilization Method
KR100929138B1 (en) * 2003-04-22 2009-12-01 엘지전자 주식회사 How to stabilize sync signal of video display device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100521942B1 (en) * 1998-08-22 2006-01-27 엘지전자 주식회사 OSD Character Stabilizer and Stabilization Method
KR100929138B1 (en) * 2003-04-22 2009-12-01 엘지전자 주식회사 How to stabilize sync signal of video display device

Also Published As

Publication number Publication date
KR0144885B1 (en) 1998-07-15

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