KR970055546A - Frequency division circuit - Google Patents
Frequency division circuit Download PDFInfo
- Publication number
- KR970055546A KR970055546A KR1019950055758A KR19950055758A KR970055546A KR 970055546 A KR970055546 A KR 970055546A KR 1019950055758 A KR1019950055758 A KR 1019950055758A KR 19950055758 A KR19950055758 A KR 19950055758A KR 970055546 A KR970055546 A KR 970055546A
- Authority
- KR
- South Korea
- Prior art keywords
- counter
- output
- frequency
- circuit
- tail
- Prior art date
Links
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- Manipulation Of Pulses (AREA)
Abstract
1. 청구 범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
주파수 분주회로를 관한 것이다.It relates to a frequency division circuit.
2. 발명이 해결하려고 하는 기술적 과제.2. The technical problem that the invention is trying to solve.
새로운 발진기의 추가없이 직접 시스템 주파수를 입력하여 N+0.5 분주하는 회로 및 상기 N+0.5분주회로를 이용하여 듀티비가 50%인 홀수배로 분주하는 회로를 제공한다.A circuit for directly inputting system frequency and adding N + 0.5 frequency divider without adding a new oscillator and using the N + 0.5 frequency divider circuit provides an odd frequency division with 50% duty ratio.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
입력주파수를 분주하는 회로는 입력주파수를 클럭원으로 하여 카운터수행하는 카운터와 상기 카운터의 출력을 입력하여 제1기간동안 선두펄스를 발생하는 선두펄스발생부와 상기 카운터의 출력을 입력하여 제2기간동안 후미펄스를 발생하는 후미펄스발생부와 상기 후미펄스발생부의 출력을 소정 지연시켜 출력하는 지연부와 상기 선두펄스 및 상기 지연부의 출력레벨을 논리곱하는 논리부로 구성한다.A circuit for dividing an input frequency inputs a counter performing a counter using the input frequency as a clock source and an output of the counter to generate a leading pulse during a first period, and inputs an output of the counter to a second period. A tail pulse generator that generates tail pulses, a delay part that delays and outputs the output of the tail pulse generator, and a logic part that logically multiplies the output level of the head pulse and the delay part.
4. 발명은 중요한 용도.4. Invention is an important use.
손쉽게 입력주파수를 N+0.5분주하기 위해 이를 구현한다.Implement this to easily divide the input frequency by N + 0.5.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 본 발명에 따른 주파수 분주회로의 실시예를 보여주는 도면.1 shows an embodiment of a frequency divider circuit according to the present invention.
제3도는 본 발명에 따른 주파수 분주회로의 또 다른 실시예를 보여주는 도면.3 is a view showing another embodiment of a frequency division circuit according to the present invention.
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950055758A KR970055546A (en) | 1995-12-23 | 1995-12-23 | Frequency division circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950055758A KR970055546A (en) | 1995-12-23 | 1995-12-23 | Frequency division circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
KR970055546A true KR970055546A (en) | 1997-07-31 |
Family
ID=66617850
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950055758A KR970055546A (en) | 1995-12-23 | 1995-12-23 | Frequency division circuit |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR970055546A (en) |
-
1995
- 1995-12-23 KR KR1019950055758A patent/KR970055546A/en not_active Application Discontinuation
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Legal Events
Date | Code | Title | Description |
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WITN | Withdrawal due to no request for examination |