KR960005607A - Synchronous Latch Circuit - Google Patents
Synchronous Latch Circuit Download PDFInfo
- Publication number
- KR960005607A KR960005607A KR1019950020895A KR19950020895A KR960005607A KR 960005607 A KR960005607 A KR 960005607A KR 1019950020895 A KR1019950020895 A KR 1019950020895A KR 19950020895 A KR19950020895 A KR 19950020895A KR 960005607 A KR960005607 A KR 960005607A
- Authority
- KR
- South Korea
- Prior art keywords
- clock
- input
- latch circuit
- data
- output
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1087—Data input latches
Abstract
[목적] 소자수 및 소비전력이 적은 동기식 래치회로를 제공한다.[Objective] A synchronous latch circuit with low number of devices and low power consumption is provided.
[구성] 동기식 래치회로는 래치부(11)와 클럭 생성부(19)에 의해 구동되고, 래치부(11)는, 입력단(210)과, 입력에 입력단(210)이 접속되고 내부 클럭(CLKP)에 의해 도통 비도통이 제어되는 트랜스퍼 게이트(180)와, 입력에 트랜스퍼 게이트(180)의 출력이 입력된 래치회로(190)와, 래치회로(190)의 출력이 입력되는 출력단(220)에 의해 구성되고, 클럭 생성부(19)와 입력되는 외부 클럭(CLKOUT)의 한쪽의 에지에 응답하여 외부 클럭(CLKOUT)과 동일 주파수임과 동시에 외부 클럭(CLKOUT)의 하이레벨 보다도 짧은 하이레벨을 갖는 내부클럭을 출력하도록 구성된다.[Configuration] The synchronous latch circuit is driven by the latch section 11 and the clock generation section 19. The latch section 11 has an input terminal 210 and an input terminal 210 connected to the input, and an internal clock CLKP. To the transfer gate 180 where the conduction non-conduction is controlled, the latch circuit 190 to which the output of the transfer gate 180 is input, and the output terminal 220 to which the output of the latch circuit 190 is input. And a high level shorter than the high level of the external clock CLKOUT at the same frequency as the external clock CLKOUT in response to one edge of the clock generator 19 and the external clock CLKOUT input thereto. It is configured to output the internal clock.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 본 발명에 동기식 래치회로의 실시예1을 나타내는 회로도.1 is a circuit diagram showing Embodiment 1 of a synchronous latch circuit according to the present invention.
Claims (4)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP94-163455 | 1994-07-15 | ||
JP6163455A JPH0832413A (en) | 1994-07-15 | 1994-07-15 | Synchronizing latch circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
KR960005607A true KR960005607A (en) | 1996-02-23 |
Family
ID=15774216
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950020895A KR960005607A (en) | 1994-07-15 | 1995-07-15 | Synchronous Latch Circuit |
Country Status (2)
Country | Link |
---|---|
JP (1) | JPH0832413A (en) |
KR (1) | KR960005607A (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100474982B1 (en) * | 1997-05-07 | 2005-06-23 | 삼성전자주식회사 | Internal Signal Generation Circuit of Synchronous Semiconductor Device |
KR100295682B1 (en) * | 1999-04-07 | 2001-07-12 | 김영환 | Data input buffer circuit |
JP5563183B2 (en) * | 2007-02-15 | 2014-07-30 | ピーエスフォー ルクスコ エスエイアールエル | Semiconductor memory integrated circuit |
KR100853649B1 (en) * | 2007-04-02 | 2008-08-25 | 삼성전자주식회사 | Clock-gated latch with a level-converting funtion |
JP5738450B2 (en) * | 2014-04-10 | 2015-06-24 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | Semiconductor memory integrated circuit |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5917719A (en) * | 1982-07-21 | 1984-01-30 | Hitachi Ltd | Cmos flip-flop circuit |
JPS59104820A (en) * | 1982-12-08 | 1984-06-16 | Hitachi Ltd | Flip-flop circuit |
JPH0814987B2 (en) * | 1985-06-21 | 1996-02-14 | 株式会社日立製作所 | Semiconductor memory device |
JPH0193916A (en) * | 1987-10-06 | 1989-04-12 | Fujitsu Ltd | Synchronous state holding circuit |
JP2708232B2 (en) * | 1989-06-23 | 1998-02-04 | 三菱電機株式会社 | Semiconductor storage device |
-
1994
- 1994-07-15 JP JP6163455A patent/JPH0832413A/en active Pending
-
1995
- 1995-07-15 KR KR1019950020895A patent/KR960005607A/en not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
JPH0832413A (en) | 1996-02-02 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E601 | Decision to refuse application |