JPH0832413A - Synchronizing latch circuit - Google Patents

Abstract

PURPOSE:To provide a synchronizing latch circuit with small component number and less power consumption. CONSTITUTION:The synchronizing latch circuit consists of a latch section 11 and a clock generating section 19, the latch section 11 is made up of an output terminal 210, a transfer gate 180 whose input connects to the input terminal 210 and whose conduction/non-conduction is controlled by. an internal clock signal, a latch circuit 190 whose input receives an output of the transfer gate 180, and an output terminal 220 receiving an output of the latch circuit 190. The clock generating section 19 provides an output of an internal clock whose frequency is the same as that of an external clock and having a smaller high level than the high level of the external clock in response to one edge of the received external clock signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous latch circuit, and more particularly to a synchronous latch circuit which performs a latch operation in synchronization with one edge of a clock.

[0002]

2. Description of the Related Art A synchronous latch circuit is required to capture input data in synchronization with one inversion edge of a clock and hold it until the next one inversion edge appears. A master / slave type is generally used as such a synchronous latch circuit.

As an address buffer to which an address of a synchronous static random access memory (synchronous SRAM) is input, an 8-bit address input buffer constituted by a master / slave synchronous latch circuit is shown in FIG. Such a synchronous latch circuit is composed of latch units 1 to 8 and a clock generation unit 9 which supplies an internal clock to each latch unit. However, since the latch units 1 to 8 have the same circuit configuration, only one latch unit 1 is shown. The latch unit 1 operates in synchronization with the internal clock CLKIN generated by the clock generation unit 9. The internal clock CLKIN is generated by delaying the external clock CLKOUT by the clock generation unit 9 configured by connecting the inverters 130 in series. Latch section 1
Is a data input terminal 10, an inverter 20 for inputting address data whose input is connected to the data input terminal, and an inverter 30 for connecting the output of the inverter 20 and further inverting the address data inverted by the inverter. , The P-type transistor and the N-type transistor are connected in parallel, the internal clock CLKIN is input to the gate of the P-type transistor, the signal obtained by inverting the internal clock CLKIN by the inverter 40 is input to the gate of the N-type transistor, and the output of the inverter 30 is input. The master in which the transfer gate 50 on the master side and the inputs and outputs of the two inverters are connected via the first node and the second node, and the output of the transfer gate 50 is input to the first node. Side latch circuit 60 and the second node of the latch circuit 60 at the input Inverter 7 output al is input
0. Further, the P-type transistor and the N-type transistor are connected in parallel, the internal clock CLKIN is input to the gate of the N-type transistor, and the signal obtained by inverting the internal clock CLKIN by the inverter 80 is input to the gate of the P-type transistor. The transfer gate 90 on the slave side to which the output is input, the latch circuit 100 on the slave side to which the output of the transfer gate 90 is input to the input by connecting the input and output of two inverters, and the latch circuit 100 to the input The inverter 110 to which the output is input and the output end 120 to which the output of the inverter 110 is input are configured.

This master / slave type synchronous latch circuit operates at the timing shown in FIG. While the internal clock CLKIN is at the low level, the transfer gate 50 on the master side becomes conductive, and the address data input to the input terminal 10 is taken into the latch circuit 60 on the master side via the inverters 20 and 30. At this time, the transfer gate 90 on the slave side is in a non-conducting state contrary to the transfer gate 50 on the master side, and the output of the latch circuit 60 on the master side becomes as shown by N in FIG. Next, when the internal clock CLKIN changes from the low level to the high level, the transfer gate 50 on the master side becomes non-conductive, while the transfer gate 90 on the slave side becomes conductive and held in the latch circuit 60 on the master side. The address data is fetched by the slave side latch circuit 100 via the inverter 70 and the transfer gate 90, and the address data fetched by the slave side latch circuit 100 is output to the output terminal 120 via the inverter 110. The address data taken into the latch circuit 100 on the slave side is kept until the transfer gate 90 on the slave side becomes conductive next time, that is, the internal clock CLK.
It is held until IN goes from low level to high level.

As described above, the two sets of latch circuits 60 and 10 are provided.
0 and two sets of transfer gates 50 and 90 are used to form a master / slave type latch unit, so that data A0 input as shown in DATA of FIG.
Even if there is a period in which other data or data is indefinite between the data A1 and the data A1, the data A0 and A1 are continuously output to the output terminal 120 as shown in OUT of FIG.
Between A1 and A1 is prevented from being output undesired data or the like.

[0006]

In the above-mentioned master / slave type synchronous latch circuit, 10 inverters and 2 sets of transfer gates are used as a latch unit for holding 1-bit data and 4 units are used as a clock generation unit. Since the number of inverters is required, and the number of bits of data to be held increases, the size of the block required to form the synchronous latch circuit inevitably increases.

Therefore, an object of the present invention is to provide a latch circuit which takes in data in synchronization with one inversion edge of a clock with a smaller number of elements and holds the acquired data until the next one inversion edge appears. It is in.

[0008]

SUMMARY OF THE INVENTION A synchronous latch circuit of the present invention is a synchronous latch circuit which takes in data in synchronization with one inversion edge of a clock, and each time the one inversion edge of the clock appears. Generates an internal clock having an inverted edge in the same direction as the one inverted edge and a period from the inverted edge to the other inverted edge is shorter than a period from the one inverted edge to the other inverted edge of the clock. Clock generating means, data holding means, and driving means inserted between the data input terminal and the data holding means for driving the data holding section based on data to the data input terminal during the period of the clock. It is characterized by having.

[0009]

As described above, since the internal clock having the inversion edge synchronized with the above-mentioned one inversion edge of the clock generator wave and having a short pulse width is generated, the master / slave method as in the prior art is used. It does not need to be taken, and is simply composed of a data holding unit and its driving unit. Therefore, the number of required elements is halved.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

A first embodiment of the present invention is shown in FIG. This embodiment is an example in which the synchronous latch circuit of the present invention is applied to an 8-bit address input buffer of a synchronous SRAM.
The synchronous latch circuit includes latch units 11 to 18 and a clock generation unit 10. Here, since the latch units 11 to 18 forming the 8-bit input buffer have the same circuit configuration, one latch unit 11 will be described. The latch unit 11 has an inverter 150 for inputting an address, the input of which is connected to the input terminal 210, and an output of the inverter 150 is connected to the input of the inverter 150.
The inverter 160 for further inverting the address data inverted by the P-type transistor and the N-type transistor are connected in parallel, and the internal clock CLKP is applied to the gate of the N-type transistor and the internal clock CLKP is applied to the gate of the P-type transistor. A transfer gate 180 to which the signal inverted by the inverter 190 is input and the output of the inverter 160 is connected to the input, and the input and output of the two inverters are connected to each other to form the transfer gate 1
80 is connected to the output of the latch circuit 190, and the input of the output of the latch circuit 190 is input to the inverter 200
And an output end 220 to which the output of the inverter 200 is input
Composed of and. The internal clock CLKP is an inverter 240 whose input is connected to the clock input terminal 310.
, An inverter 250 having an input connected to the output of the inverter 240, a NAND circuit 290 having one input connected to the output of the inverter 250, and an odd number (in between the inverter 250 and the other input of the NAND circuit 290). In this embodiment, three inverters 260 and 2 are connected in series.
70 and 280, an inverter circuit 300 having an input connected to the output of the NAND circuit 290, and an inverter circuit 30.
The output of 0 is generated by the clock generation unit 19 configured by the clock output terminal 320 to which the output of 0 is connected.

The operation of the synchronous latch circuit of the present invention is shown in FIG.
Is shown in the timing chart of. The clock generation unit 19 that supplies the internal clock CLKP to the latch unit 11 responds to the rising edge of the input clock CLKOUT and has the same frequency as the clock CLKOUT, and the delay time obtained by the inverters 260, 270, and 280. The internal clock CLKP having a high level period defined by is output. Internal clock CLKP
The high level period of is the period from the rising edge to the falling edge of the clock CLKOUT input by adjusting the delay time obtained from the inverter by changing the number of inverters,
It is set shorter than the high level period of the input clock CLKOUT. The latch unit 11 holds and outputs the address data input to the input end 210 in response to the internal clock CLKP generated by the clock generation unit 19. That is, when the internal clock CLKP rises to high level, the transfer gate 1
80 becomes conductive and transmits the address data input to the input terminal 210 to the latch circuit 190. The latch circuit 190 fetches the address data and outputs the fetched address data to the output end 220 via the inverter 200. Next, when the internal clock CLKP falls and goes from the high level to the low level, the transfer gate 180 becomes non-conductive and does not transmit the address data of the input terminal 210 to the latch circuit 190.
Hold the fetched address data. Therefore, the address data taken in when the internal clock CLKP is at the high level is held by the latch circuit 190 until the internal clock CLKP next goes to the high level. In this way, the data output to the output terminal 220 becomes the data taken in when the internal clock CLKP is at the high level, and new data is held in the latch circuit 190 when the internal clock CLKP next becomes the high level. Does not change until Therefore, a synchronous latch circuit that operates similarly to the master-slave type synchronous latch circuit is provided with 6 inverters and 1 transfer gate as a latch unit, 6 inverters and 1 NAND as a clock generating unit. It can be composed of a circuit.

A second embodiment of the present invention is shown in FIG. This embodiment is an example in which the present invention is applied to an 8-bit output buffer in a synchronous SRAM. The synchronous latch circuit is composed of latch units 21 to 28 and a clock generation unit 19. Here, since the eight latch units 21 to 28 forming the 8-bit output buffer have the same configuration,
One latch unit 21 will be described. However, the description of the clock generator 19 that generates the internal clock CLKP is omitted.

The latch section 21 has an input terminal 330, to which output data is input, and a P-type transistor and an N-type transistor connected in parallel. The internal clock CLKP is supplied to the gate of the N-type transistor, and the internal clock is supplied to the gate of the P-type transistor. A transfer gate 350 to which a signal obtained by inverting the clock CLKP by the inverter 340 is input and whose input is connected to the input terminal 330, and a latch to which the input and output of two inverters are connected and the output of the transfer gate 350 is connected to the input A circuit 360, an inverter 370 to which the output of the latch circuit 360 is connected, an output of the inverter 370 to one input, and a control signal OEC supplied from a control circuit (not shown) to the other input N input via the 480 and the inverter 400
An AND circuit 380 and a NOR circuit 390 to which the output of the inverter 370 is input to one input and the control signal OEC supplied from a control circuit (not shown) is input to the other input.
And the output of the NAND circuit 380 is input to the gate and Vd
By the P-type MOS transistor 410 provided between the output d and the output terminal and the N-type MOS transistor 420 provided between the output terminal 430 and the ground (GND), the output of the NOR circuit 390 is input to the gate. Composed.

The operation of this synchronous latch circuit is shown in FIG. The operation is basically the same as that shown in the first embodiment, but since it is used for the output buffer, it is necessary to drive the load connected to the output end 430 with a large capacity, The generated data controls the activation and deactivation of the NAND circuit 380 and the NOR circuit 390 by the control signal supplied to the control signal input terminal 470 of the driving transistors 410 and 420, and outputs the output terminal when activated. Output data is output to 430, and when it is inactivated, the output terminal 430 is set to high impedance (H
i-z) is different.

In the present invention, the clock generator which generates the internal clock in response to the rising edge has been described as an example, but the internal clock may be generated in response to the falling edge. Further, although the clock generation unit is configured by the inverter (delay circuit) and the NAND circuit, any circuit having a configuration that detects one inversion edge of the clock may be used. Furthermore, although the present invention has been described by taking the input / output buffer of the synchronous SRAM as an example, the present invention is not limited to various types as long as input / output is performed in response to a clock without departing from the gist of the present invention. It goes without saying that changes and applications are possible.

[0017]

As described above, the latch section is composed of six inverters and one latch circuit, and the internal clock for controlling the operation of the circuit is detected by detecting the rising edge of the input clock. By using a clock generator that generates pulses in response to edges, the number of elements in the synchronous latch circuit can be reduced without changing the input / output characteristics, and the block size and power consumption can be reduced. be able to.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a synchronous latch circuit of the present invention.

FIG. 2 is a timing chart showing the operation of the first embodiment of the synchronous latch circuit of the present invention.

FIG. 3 is a circuit diagram showing a second embodiment of the synchronous latch circuit of the present invention.

FIG. 4 is a timing chart showing the operation of the second embodiment of the synchronous latch circuit of the present invention.

FIG. 5 is a circuit diagram of a conventional synchronous latch circuit.

FIG. 6 is a timing chart showing the operation of a conventional synchronous latch circuit.

[Explanation of symbols]

1, 2, 3, 4, 5, 6, 7, 8, 11, 12, 13,
14, 15, 16, 17, 18, 21, 22, 23, 2
4, 25, 26, 27, 28 Latch unit 19 Clock generation unit 10, 210, 330 Input end 120, 220, 430 Output end 310, 440 External clock input end 320, 450 Internal clock output end 140, 230, 460 Internal clock Input terminal 470 Control signal input terminal 20, 30, 40, 70, 80, 110, 130, 15
0, 160, 170, 200, 240, 250, 26
0, 270, 280, 300, 340, 370, 400
Inverter 50, 90, 180, 350 Transfer gate 290, 380 NAND circuit 390 NOR circuit 410 P-type MOS transistor 420 N-type MOS transistor

Claims (4)

[Claims] 1. A synchronous latch circuit for fetching data in synchronization with one inversion edge of a clock, wherein an inversion edge in the same direction as the one inversion edge appears every time the one inversion edge of the clock appears. And a clock generation means for generating an internal clock in which the period from the inversion edge to the other inversion edge is shorter than the period from the one inversion edge to the other inversion edge of the clock,
It has a data holding means and a driving means inserted between the data input terminal and the data holding means and driving the data holding part based on the data to the data input terminal during the period of the clock. Synchronous latch circuit. 2. The clock means has a gate circuit which receives the clock at one input and receives the clock delayed from the clock at the other input to generate the internal clock. 1. The synchronous latch circuit according to 1. 3. The synchronous latch circuit according to claim 1, wherein the driving means has a transfer gate in which the internal clock is turned on during the period. 4. The data holding means includes first and second inverters, one input and one output of which are connected to the other output and input, respectively. Synchronous latch circuit.