KR970062869A - Internal clock generation method for output buffer - Google Patents

Internal clock generation method for output buffer Download PDF

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Publication number
KR970062869A
KR970062869A KR1019960003309A KR19960003309A KR970062869A KR 970062869 A KR970062869 A KR 970062869A KR 1019960003309 A KR1019960003309 A KR 1019960003309A KR 19960003309 A KR19960003309 A KR 19960003309A KR 970062869 A KR970062869 A KR 970062869A
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KR
South Korea
Prior art keywords
internal clock
output buffer
generating
edge
predetermined width
Prior art date
Application number
KR1019960003309A
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Korean (ko)
Other versions
KR100200925B1 (en
Inventor
이정배
서동일
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960003309A priority Critical patent/KR100200925B1/en
Publication of KR970062869A publication Critical patent/KR970062869A/en
Application granted granted Critical
Publication of KR100200925B1 publication Critical patent/KR100200925B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)

Abstract

1. 청구 범위에 기재된 발명이 속한 기술분야1. Technical field to which the invention described in the claims belongs

반도체 메모리 장치에 관한 것이다.To a semiconductor memory device.

2. 발명이 해결하려고 하는 기술적 과제2. Technical Challenges to be Solved by the Invention

전력 소모와 비용을 줄일 수 있는 출력버퍼용 내부클럭 생성방볍을 제공함에 있다.And an internal clock generation method for the output buffer that can reduce power consumption and cost.

3. 발명의 해결방법의 요지3. The point of the solution of the invention

외부클럭에 동기되어 동작하는 반도체 메모리 장치의 출력버퍼를 구동하기 위한 내부클럭의 생성방법에 있어서; 상기 외부클럭의 제1에지에 응답하여 제1소정폭을 가지는 제1펄스를 생성하는 과정과, 상기 제1펄스의 제2에지에 응답하여 제2소정폭을 가지는 상기 내부클럭을 생성하는 과정으로 이루어짐을 특징으로 한다.A method of generating an internal clock for driving an output buffer of a semiconductor memory device operating in synchronization with an external clock, the method comprising: Generating a first pulse having a first predetermined width in response to a first edge of the external clock; and generating the internal clock having a second predetermined width in response to a second edge of the first pulse, .

4. 발명의 중요한 용도4. Important Uses of the Invention

반도체 메모리 장치에 적합하게 사용된다.And is suitably used for a semiconductor memory device.

Description

출력버퍼용 내부클럭 생성방법Internal clock generation method for output buffer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제3도는 본 발명에 따라 구성된 타이밍도.Figure 3 is a timing diagram constructed in accordance with the present invention;

제4도는 본 발명의 실시예에 따라 구성된 펄스발생기들의 구체회로도.4 is a specific circuit diagram of pulse generators constructed in accordance with an embodiment of the present invention.

제5도는 본 발명에 따라 지연시간을 조절하기 위한 회로 블럭도.FIG. 5 is a circuit block diagram for adjusting the delay time according to the present invention; FIG.

Claims (4)

외부클럭에 동기되어 동작하는 반도체 메모리 장치의 출력버퍼를 구동하기 위한 내부클럭의 생성방법에 있어서; 상기 외부클럭의 제1에지에 응답하여 제1소정폭을 가지는 제1펄스를 생성하는 과정과, 상기 제1펄스의 제2에지에 응답하여 제2소정폭을 가지는 상기 내부클럭을 생성하는 과정으로 이루어짐을 특징으로 하는 방법.A method of generating an internal clock for driving an output buffer of a semiconductor memory device operating in synchronization with an external clock, the method comprising: Generating a first pulse having a first predetermined width in response to a first edge of the external clock; and generating the internal clock having a second predetermined width in response to a second edge of the first pulse, ≪ / RTI > 제1항에 있어서, 상기 제1에지와 제2에지에는 폴링에지임을 특징으로 하는 방법.2. The method of claim 1, wherein the first edge and the second edge are polling edges. 제1항에 있어서, 상기 제1소정폭은 동작주파수에 따라 결정됨을 특징으로 하는 방법.2. The method of claim 1, wherein the first predetermined width is determined according to an operating frequency. 제1항에 있어서, 상기 제1소정폭은 홀수배 증가되는 인버터들에 의해 결정됨을 특징으로 하는 방법.The method of claim 1, wherein the first predetermined width is determined by inverters that are multiplied by an odd multiple. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960003309A 1996-02-12 1996-02-12 Internal clock generation method for output buffer KR100200925B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960003309A KR100200925B1 (en) 1996-02-12 1996-02-12 Internal clock generation method for output buffer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960003309A KR100200925B1 (en) 1996-02-12 1996-02-12 Internal clock generation method for output buffer

Publications (2)

Publication Number Publication Date
KR970062869A true KR970062869A (en) 1997-09-12
KR100200925B1 KR100200925B1 (en) 1999-06-15

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Application Number Title Priority Date Filing Date
KR1019960003309A KR100200925B1 (en) 1996-02-12 1996-02-12 Internal clock generation method for output buffer

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101413173B1 (en) * 2012-12-14 2014-07-21 주식회사 파세코 Control Device Electric Power for Electric Range

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101413173B1 (en) * 2012-12-14 2014-07-21 주식회사 파세코 Control Device Electric Power for Electric Range

Also Published As

Publication number Publication date
KR100200925B1 (en) 1999-06-15

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