KR970071819A - Clock Suspension Guarantee Circuit of Synchronous Semiconductor Memory Device - Google Patents

Clock Suspension Guarantee Circuit of Synchronous Semiconductor Memory Device Download PDF

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Publication number
KR970071819A
KR970071819A KR1019960012699A KR19960012699A KR970071819A KR 970071819 A KR970071819 A KR 970071819A KR 1019960012699 A KR1019960012699 A KR 1019960012699A KR 19960012699 A KR19960012699 A KR 19960012699A KR 970071819 A KR970071819 A KR 970071819A
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South Korea
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signal
latency
clock
unit
delay
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KR1019960012699A
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Korean (ko)
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KR0184479B1 (en
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이상길
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김광호
삼성전자 주식회사
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

1. 청구 범위에 기재된 발명이 속한 기술분야1. Technical field to which the invention described in the claims belongs

동기형 반도체 메모리장치.Synchronous semiconductor memory device.

2. 발명이 해결하려고 하는 기술적 과제2. Technical Challenges to be Solved by the Invention

동기형 반도체 메모리장치의 클럭 서스펜션 보장회로를 제공한다.A clock suspension assurance circuit of a synchronous semiconductor memory device is provided.

2. 발명의 해결방법의 요지2. The point of the solution of the invention

동기형 반도체 메모리 장치에서 프리차아지 동작후 클럭 서스펜션을 보장하기 위한 회로는, 상기 클럭 서스펜션을 보장하는 레이턴시 신호를 소정의 시간동안 지연하여 지연 레이턴시 신호를 생성하는 지연 레이턴시부를 구비함을 특징으로 한다.A circuit for ensuring a clock suspension after a precharging operation in a synchronous semiconductor memory device includes a delay latency unit for delaying a latency signal for ensuring the clock suspension for a predetermined time to generate a delay latency signal .

4. 발명의 중요한 용도4. Important Uses of the Invention

동기형 반도체 메모리장치의 클럭 서스펜션 보장회로.A clock suspension assurance circuit for a synchronous semiconductor memory device.

Description

동기형 반도체 메모리장치의 클럭 서스펜션 보장회로Clock Suspension Guarantee Circuit of Synchronous Semiconductor Memory Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제6도는 본 발명의 일실시예에 따른 클럭발생 관련 블럭도, 제7도는 제6도중 지연 레이턴시부 400의 일실시예에 따른 구체회로도.FIG. 6 is a block diagram of a clock generation related block diagram according to an embodiment of the present invention, and FIG. 7 is a specific circuit diagram according to an embodiment of the delay latency unit 400 of FIG.

Claims (5)

동기형 반도체 메모리 장치에서 프리차아지 동작후 클럭 서스펜션을 보장하기 위한 회로에 있어서, 상기 클럭 서스펜션을 보장하는 레이턴시 신호를 소정의 시간동안 지연하여 지연 레이턴시 신호를 생성하는 지연 레이턴시부를 구비함을 특징으로 하는 회로.A circuit for ensuring a clock suspension after a precharging operation in a synchronous semiconductor memory device, the circuit comprising: a delay latency unit for delaying a latency signal for ensuring the clock suspension for a predetermined time to generate a delay latency signal; Circuit. 제1항에 있어서, 상기 지연 레이턴시부는 내부클럭과 제3및 4카스 레이턴시를 조합하여 내부 스위칭 신호를 발생하는 스위칭 신호 발생유닛과, 상기 레이턴시 신호를 상기 내부 스위칭신호에 응답하여 전송하는 전송유닛과, 상기 전송유닛을 통해 출력되는 상기 레이턴시 신호를 래치하여 상기 지연 레이턴시 신호를 출력하는 래치유닛을 구비함을 특징으로 하는 회로.2. The apparatus of claim 1, wherein the delay latency unit comprises: a switching signal generation unit for generating an internal switching signal by combining an internal clock and third and fourth cache latency; a transmission unit for transmitting the latency signal in response to the internal switching signal; And a latch unit for latching the latency signal output through the transmission unit and outputting the delay latency signal. 동기형 다이나막 억세스 메모리 장치에서 클럭 서스펜션을 보장하기 위한 회로에 있어서; 클럭 인에이블 신호에 응답하여 인가되는 외부클럭을 필요한 내부클럭으로 변환출력하고, 출력신호를 인가하기 위한 클럭버퍼와; 상기 클럭버퍼로부터 출력되는 상기 내부클럭과, 제1-4카스 레이턴시, 및 선택된 뱅크에서 제공되는 신호를 수신하여 레이턴시 신호를 출력하는 레이턴시부와; 상기 레이턴시부에 접속되며, 프리차아지 동작후 클럭 서스펜션을 보장하기 위하여 상기 레이턴시 신호를 내부클럭의 반클럭에 대응되는 신간만큼 지연한 지연 레이턴시 신호를 생성하기 위한 지연 레이턴시부와; 상기 지연 레이턴시부의 지연 레이턴시 신호 및 상기 클럭 신호를 수신하여 상기 클럭버퍼의 동작을 인에이블 또는 디스에이블시키기 위한 상기 클럭 인에이블 신호를 발생하기 위한 클럭 인에이블 버퍼를 구비함을 특징으로 하는 회로.CLAIMS What is claimed is: 1. A circuit for assuring a clock suspension in a synchronous dynamic access memory device, comprising: A clock buffer for converting an external clock applied in response to a clock enable signal into a necessary internal clock and applying an output signal; A latency unit receiving the internal clock output from the clock buffer, the 1 st to 4 kth latency, and the signal provided from the selected bank and outputting a latency signal; A delay latency unit connected to the latency unit for generating a delay latency signal delayed by a new period corresponding to a half clock of the internal clock signal to ensure a clock suspension after a precharging operation; And a clock enable buffer for receiving the delay latency signal and the clock signal of the delay latency portion to generate the clock enable signal to enable or disable the operation of the clock buffer. 제3항에 있어서, 상기 지연 레이턴시부는, 상기 내부클럭과 제3 및 제4카스 레이턴시를 조합하여 내부 스위칭 신호를 발생하는 스위칭 신호 발생유닛과, 상기 레이턴시 신호를 상기 내부 스위칭신호에 응답하여 전송하는 전송유닛과, 상기 전송유닛을 통해 출력되는 상기 레이턴시 신호를 래치하여 상기 지연 레이턴시 신호를 출력하는 래치유닛을 구비함을 특징으로 하는 회로.The apparatus as claimed in claim 3, wherein the delay latency unit comprises: a switching signal generating unit for generating an internal switching signal by combining the internal clock and the third and fourth cache latency; and a switching signal generating unit for transmitting the latency signal in response to the internal switching signal And a latch unit for latching the latency signal output through the transmission unit and outputting the delay latency signal. 동기형 반도체 메모리 장치에서 프리차아지 동작후 클럭 서스펜션을 보장하기 위한 방법에 있어서, 상기 클럭 서스펜션을 보장하는 레이턴시 신호를 소정의 시간동안 지연하여 지연 레이턴시 신호를 생성하고 이를 상기 클럭 서스펜션을 보장하기 위한 신호로서 사용함을 특징으로 하는 방법.A method for ensuring a clock suspension after a precharging operation in a synchronous semiconductor memory device, the method comprising: generating a delay latency signal by delaying the latency signal for ensuring the clock suspension for a predetermined time, Signal. ≪ / RTI > ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960012699A 1996-04-24 1996-04-24 Synchronous memory device KR0184479B1 (en)

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KR0184479B1 KR0184479B1 (en) 1999-04-15

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KR100866958B1 (en) 2007-02-08 2008-11-05 삼성전자주식회사 Method and apparatus for controlling read latency in high speed DRAM

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