KR970024608A - Frequency conversion method and circuit of clock pulse - Google Patents
Frequency conversion method and circuit of clock pulse Download PDFInfo
- Publication number
- KR970024608A KR970024608A KR1019950035860A KR19950035860A KR970024608A KR 970024608 A KR970024608 A KR 970024608A KR 1019950035860 A KR1019950035860 A KR 1019950035860A KR 19950035860 A KR19950035860 A KR 19950035860A KR 970024608 A KR970024608 A KR 970024608A
- Authority
- KR
- South Korea
- Prior art keywords
- clock pulse
- frequency
- circuit
- frequency conversion
- input data
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
Abstract
본 발명은 클럭펄스(Clock pulse)의 주파수 변환방법 및 회로에 관한 것으로서, 적용될 주파수 범위에서 최대 주파수의 제1클럭 펄스(Clock pulse)를 발생시키는 클럭 펄스 발생기 ; 상기 제1클럭 펄스를 계수(Count)하여, 상기 계수값(Count value)이 입력 데이터와 같을 때마다 한 개의 제2클럭 펄스를 발생시키는 펄스 계수기 ; 및 상기 제2클럭 펄스의 주파수를 2분주시키는 2분주기 ; 를 포함한 것을 그 특징으로 하여, 적용 시스템의 마이크로프로세서에 의하여 해당 모터 제어기 (Motor controller)에 인가될 클럭 펄스의 주파수를 제어할 수 있음에 따라, 모터 제어기가 적용된 시스템의 생산성을 높일 수 있다.The present invention relates to a frequency conversion method and circuit of a clock pulse, the clock pulse generator for generating a first clock pulse (Clock pulse) of the maximum frequency in the frequency range to be applied; A pulse counter for counting the first clock pulse to generate a second clock pulse each time the count value is equal to input data; And a divider for dividing the frequency of the second clock pulse by two. Characterized in that it can be, by controlling the frequency of the clock pulse to be applied to the motor controller (Motor controller) by the microprocessor of the application system, it is possible to increase the productivity of the system to which the motor controller is applied.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제1도는 본 발명에 따라서, 입력 데이터가 ‘4’인 경우의 주파수 변환방법을 나타낸 타이밍도,1 is a timing diagram showing a frequency conversion method when the input data is '4' according to the present invention;
제2도는 제1도의 주파수 변환방법을 구현하기 위한 회로도이다.2 is a circuit diagram for implementing the frequency conversion method of FIG.
Claims (7)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950035860A KR0183747B1 (en) | 1995-10-17 | 1995-10-17 | Frequency conversion method of clock pulse |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950035860A KR0183747B1 (en) | 1995-10-17 | 1995-10-17 | Frequency conversion method of clock pulse |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970024608A true KR970024608A (en) | 1997-05-30 |
KR0183747B1 KR0183747B1 (en) | 1999-04-15 |
Family
ID=19430465
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950035860A KR0183747B1 (en) | 1995-10-17 | 1995-10-17 | Frequency conversion method of clock pulse |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0183747B1 (en) |
-
1995
- 1995-10-17 KR KR1019950035860A patent/KR0183747B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR0183747B1 (en) | 1999-04-15 |
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