JPH01251916A - Multiphase pulse generating circuit - Google Patents

Abstract

PURPOSE:To reduce the size and cost of the title circuit without using any high-speed device by respectively synthesizing single reference pulses and the 2nd reference pulses produced by inverting the reference pulses in corresponding to the numbers of stages of frequency dividers and inputting the synthesized reference pulses to the clock (CK) terminals of the frequency dividers. CONSTITUTION:Not only single reference pulses (a), but also inverted reference pulses (b) produced by inverting the reference pulses (a) are prepared and both reference signals (a) and (b) are respectively synthesized in corresponding to the numbers of stages of frequency dividers 2a, 2b,... and the synthesized reference pulses 1, 2, etc., are inputted to the CK input terminals of the frequency dividers. Therefore, the reference pulses (a) can be inverted at both triggering moments of rising and falling and the frequency of the pulses (a) can be set at the 1/2 as compared with the conventional example. Thus this multiphase pulse generation circuit can be reduced in size and cost.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a multiphase pulse generation circuit formed by sequentially dividing a reference input signal pulse with a phase difference.

"Prior Art" Conventionally, for example, as shown in FIGS. 4(a) and 4(b), there has been a clock generator l which generates a rectangular wave-like clock pulse (i), or in other words, a rectangular-wave reference pulse having a constant frequency.
It consists of a plurality of flip-flops (hereinafter referred to as F/F circuits) that function as frequency dividers 2a... connected in a multi-stage manner, and the clock pulses are passed through the F/F circuits 2a and 2a of each stage.
..., when the clock pulse ■ rises or falls, the F of each stage
True output terminal Q and negative output terminal Q of /F circuit 2a...
A circuit that generates rectangular wave-like multiphase pulses (1) to (2) formed by successively dividing the clock pulse (1) with a phase difference by utilizing the inversion of the output signal of the clock pulse (2) is already well known.

Based on the multiphase pulses generated in this way, a multiphase clock signal, etc., which plays the role of the heart as a reference signal for microcomputers and other devices, is generated. With the increase in the capacity of stored information, there is an increasing demand for faster cycle times and higher constant speeds of the multiphase clock signals.

"Problems to be Solved by the Invention" However, in the multiphase pulse generation circuit, the frequency division period of the multiphase pulses If n is the number of stages of the F/F circuit 2a..., then it becomes 1/2n of the period of the input clock pulse, so for example, as shown in FIG. If you try to generate a six-phase pulse with
This results in an extremely high frequency.

Therefore, in order to operate the circuit at such a high frequency, it is not only necessary to use high-speed devices, but also the power consumption of the circuit increases, and more unnecessary radio waves are emitted, and it is necessary to suppress them and increase the speed constant. The control circuit for this purpose also becomes complicated, which goes against the demands for miniaturization and cost reduction.

In view of such demands, the present invention can easily achieve high-speed periodization and high-constant speed of multiphase pulses obtained by frequency-dividing input pulses, without increasing the frequency of input pulses that serve as a reference. The purpose is to provide a multiphase pulse generation circuit.

"Means for Solving the Problem" In order to achieve the technical problem, the present invention provides a reference signal generator l that generates a reference pulse having a constant frequency such as a clock pulse ■, and a reference signal generator l that generates the reference pulse ■. The point that an inverter 4 is provided to generate an inverted inverted reference pulse (■).

■Other frequency dividers 2a..., 3a... connected in multiple stages
. . , and the frequency divider 2a . . . , 3a .
A point in which a synthetic reference pulse generating means 5a for alternately outputting (as is or inverted)... is provided. Each of the synthetic reference pulses output from the nucleus generating means 5a... is connected to a corresponding frequency divider. By inputting to the reference pulse input terminals CK of 2a..., 3a..., a multiphase pulse is generated in which each rise or fall of the reference pulses is divided with a phase difference corresponding to the retrigger. We propose a multiphase pulse generation circuit characterized by the following features:

The frequency dividers 2a, 3a, . . . are generally constructed of flip-flops, but are not limited to this, and may also be constructed using multivibrators or the like.

Further, the reference pulse input terminal CK generally refers to a clock input terminal (hereinafter referred to as a GK terminal).

Further, the synthetic reference pulse generating means 5a... can be easily constituted by a logic circuit consisting of a combination of AND gates, NOR gates, and the like.

"Function" Frequency divider 2a composed of conventional flip-flops, etc.
..., 3a... is that the inversion of the output signals from the output terminals (Q and Q) forming multiphase pulses is
The point is that the reference pulse (2) input to the K terminal rises or falls only in response to a trigger in one direction of the retrigger, and cannot be reversed in response to both triggers.

Therefore, when trying to generate a six-phase multiphase pulse, for example, the frequency of the reference pulse (■) becomes eight times the division period of the multiphase pulse, corresponding to the number of phase differences of the multiphase pulse, resulting in The frequency becomes extremely high.

For this reason, the present invention provides not only a single reference pulse (2) as in the prior art, but also an inverted reference pulse (2) which is an inversion of the reference pulse (2), and both reference pulses (2) are passed through the frequency divider 2a.
..., 3a..., and input the synthesized reference pulses ■ to ■ to the CK terminal, resulting in both the rising and falling triggers of the reference pulse ■. It is possible to construct a multiphase pulse generation circuit that can invert any of the following, and thereby the frequency of the reference pulse (2) can be set to 1/2 compared to the conventional one.

Furthermore, as shown in FIG. 3, the present invention provides, for example, a group of JK-F/F circuits 3a (frequency divider) that inverts at the falling edge of the synthetic reference pulses 1 to 3, and a D-F/F circuit 3a that inverts at the rising edge of the synthetic reference pulses.
A group of F/F circuits 2 and 2... (frequency dividers) are arranged in parallel, and synthetic reference pulses ■ to ■ corresponding to each stage of F/F circuits 2a..., 3a... (frequency dividers) are generated. By configuring it to be input, different pulses can be generated for both the rising and falling triggers of the synthesis reference pulses (1) to (2).

"Embodiments" Hereinafter, preferred embodiments of the present invention will be described in detail by way of example with reference to the drawings. However, unless otherwise specified, the dimensions, materials, shapes, and relative arrangements of the components described in this example are not intended to limit the scope of this invention, but are merely illustrative examples. It's nothing more than that.

Figure 1 (&) (b) shows D-flip, p-flop (hereinafter D-F
A multiphase pulse generation circuit according to an embodiment of the present invention in which a frequency divider is configured using an F/F circuit (referred to as an F/F circuit), which includes a clock generator l that generates a clock pulse ■;
An inverter 4 for inverting the clock pulse (2), a group of D-F/F circuits 2a connected in a multistage manner, and the D-F/F
It consists of synthetic pulse generating means 5a, which are arranged on the input side of the circuits 2a, respectively.

The synthesized pulse generating means 5a .
A...'s Q output signal is guided to the input terminal, and when these old or low signals match, the other AND gate 7 outputs the corresponding signal, and any one of these AND gates B and 7 is connected to the input terminal. It is composed of a - NOR gate 8 that inverts the old or low output signal when it is input and outputs the synthetic reference pulses (1) to (4) of a predetermined period.

On the other hand, as is well known, the D-F/F circuit 2a... is equipped with a data input terminal (D input terminal), an input terminal at C, and Q and Q output terminals, and detects the rising edge of the signal input to the GK input terminal. It is a circuit in which the Q and Q output signals are inverted at times,
And the above-mentioned synthetic reference pulse ■ is applied to the GK input terminal.
In addition, the Q output signals of the D-F/F circuit 2a... in this installation are respectively input to the input terminals, and as mentioned above, the Q and Q output signals are input to the input terminals. The signals are input to the AND gates θ and 7 at the next stage, respectively.

According to this configuration, each of the synthesis reference pulse generation means 5
The output signal from the NOR gate 8 at a... is a state in which the pulses of every three cycles of the clock pulse ■ and every three cycles of the inverted clock pulse ■ are inverted, in other words, D
-F/F circuit 2a... It is possible to output both the clock pulses (2) in an alternately inverted state at cycle intervals selected according to the number of stages in the group, and as a result, (2) in FIG. 1(b)
The waveform shown in ■■ will be obtained.

When the waveforms shown in ■■■ are integrated, a waveform is obtained in which the clock pulse (■) and the inverted clock pulse (■) are integrated.

Therefore, D of each stage to which such synthetic reference pulses ■ to ■ correspond
- When inputted to the CK input terminal of the F/F circuit 2a..., the Q and Q output signals are inverted in response to the rising trigger of the synthesis reference pulses ■ to ■, and each of the synthesis reference pulses ■, ■, and From the reference pulses ■～■, divided pulse waveforms of ■ and ■, ■ and ■, and ■ and ■ are output, respectively, and these are ■−■−
A frequency divider is constructed using an F/F circuit called a six-phase multiphase pulse (hereinafter referred to as JK-F/Flll path) whose phase is shifted by π/3 in the order of ■−■−■−■. 1 is a constructed multiphase pulse generation circuit according to an embodiment of the present invention.

As is well known, the JK-F/F circuit 3a... includes a pair of input terminals (input terminal to J), a GK input terminal, and Q and Q output terminals, and the D-F/F circuit 2a...・Conversely, this is a circuit in which the Q and Q output signals are inverted when the signal input to the GK input terminal falls, and each G
The above-mentioned synthetic reference pulses ■～■ are also connected to the K input terminal.
A circuit voltage is applied to the input terminal of J of the JK-F/F circuit 3a on the stage side, and on the other hand, the input terminal of J of the JK-F/F circuit 3a of the previous stage side is applied to the input terminal of J of the JK-F/F circuit 3a of the stage side. . . , the Q and Q output signals are respectively inputted.

Therefore, in this embodiment as well, as in the previous embodiment, when the synthetic reference pulses ■ to ■ are input to the CK input terminals of the JK-F/F circuits 3a of the corresponding stages, the synthetic reference pulses ■ The Q and Q output signals are inverted in response to the falling trigger of ~■, and from the composite reference pulses ■~■ of ■, ■, and ■, respectively, ■゛ and ■'', ■°, ■゛, ■° and ■”
The divided pulse waveforms of are output, and these are ■′−
It is formed as a six-phase multiphase pulse whose phase is shifted by π/3 in the order of ■° - ■° - ■° - ■° - ■°, and the effects of the present invention can be smoothly achieved.

Incidentally, as shown in FIG. 3, the JK-F/F circuit 3a.
... group and the D-F/F circuit 2a... group are arranged in parallel and each of the synthesis reference pulses (■, ■, and ■) is applied to each corresponding GK input terminal, respectively, the JK- F
/F circuits 3a... group, the fall of the synthetic reference pulses ■ to ■ corresponds to the retrigger, and the Q and Q output signals are inverted, and in the D-F/F circuits 2a... group, the synthetic reference pulses ■ - ■ are inverted. ~■
Since the Q and Q output signals are inverted in response to a rising trigger, pulses with different phases can also be generated.

"Effects of the Invention" As described above, according to the present invention, not only a single reference pulse but also a second reference pulse obtained by inverting the reference pulse is prepared, and both reference pulses are divided into stages of a frequency divider. By inputting the synthesized reference pulse to the CK terminal of the frequency divider, it is possible to increase the periodicity of multiphase pulses as the integration of LSIs increases and the capacity of stored information increases. Even if this is achieved, a reference pulse having a frequency that is a low multiple of 172 of the phase shift number can be used, without having to multiply the reference pulse according to the phase shift number as in the past.
As a result, there is no need to use high-speed devices, and as a result, reduction in power consumption, size, and cost of the circuit can be easily achieved.

Furthermore, since the second reference pulse is not generated separately from the first reference pulse, but is simply an inversion of the first reference pulse, its rise and fall timings are symmetrical and accurate. As a result, there is no room for phase errors to occur on the output multiphase pulse side, and high constant speed can be easily achieved.The inverter, composite pulse generation means, and frequency divider are all combinations of logic circuits. Easily constructed by Figure 1(a),
FIG. 2(a) and FIG. 3(a) are both block diagrams showing a multiphase pulse generation circuit according to an embodiment of the present invention.

FIG. 1(b), FIG. 2(b), and FIG. 3(b) are time charts of the corresponding multiphase pulse generation circuits.

FIGS. 4(a) and 4(b) are a block diagram and a time chart showing a multiphase pulse generation circuit according to the prior art.

Claims (1)

[Claims] 1) A reference signal generator that generates a reference pulse having a constant frequency, an inverter that generates an inverted reference pulse by inverting the reference pulse, and a group of frequency dividers connected in a multistage manner. , a composite reference pulse generating means for alternately outputting both the reference pulses at cycle intervals selected according to the number of stages of the frequency divider group, and the composite reference pulse is input as a reference pulse to each corresponding frequency divider. A multiphase pulse generation circuit, characterized in that, by inputting it to a terminal, a multiphase pulse generated by frequency division with a phase difference corresponding to each rising or falling trigger of both of the reference pulses or both triggers is generated. 2) A frequency divider group that inverts when the synthetic reference pulse falls and a frequency divider group that inverts when the synthetic reference pulse rises are arranged in parallel, and each synthesized reference pulse corresponding to each stage is inputted to each frequency divider. The multiphase pulse generation circuit according to claim 1), characterized in that: