KR970054242A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
KR970054242A
KR970054242A KR1019950065644A KR19950065644A KR970054242A KR 970054242 A KR970054242 A KR 970054242A KR 1019950065644 A KR1019950065644 A KR 1019950065644A KR 19950065644 A KR19950065644 A KR 19950065644A KR 970054242 A KR970054242 A KR 970054242A
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KR
South Korea
Prior art keywords
layer
forming
film
polysilicon layer
high voltage
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KR1019950065644A
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Korean (ko)
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KR100193892B1 (en
Inventor
우상호
김재옥
은용석
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019950065644A priority Critical patent/KR100193892B1/en
Publication of KR970054242A publication Critical patent/KR970054242A/en
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Publication of KR100193892B1 publication Critical patent/KR100193892B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing

Abstract

본 발명은 반도체 소자의 제조방법을 제공하는 것으로, 실리콘기판상에 폴리실리콘층 및 유전체층을 형성하고, 그 위에 희생 폴리실리콘층을 형성하여 후속공정시 상기 유전체층을 보호하므로써 소자의 수율을 향상시킬 수 있는 효과가 있다.The present invention provides a method for manufacturing a semiconductor device, by forming a polysilicon layer and a dielectric layer on a silicon substrate, and forming a sacrificial polysilicon layer thereon to protect the dielectric layer in subsequent processes to improve the yield of the device It has an effect.

Description

반도체 소자의 제조방법Manufacturing method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1e도는 본 발명에 따른 반도체 소자의 제조방법을 설명하기 위한 소자의 단면도.1E is a cross-sectional view of a device for explaining a method of manufacturing a semiconductor device in accordance with the present invention.

Claims (7)

반도체 소자의 제조방법에 있어서, 필드산화막이 형성된 실리콘기판상에 터널산화막 및 폴리실리콘층을 형성하는 단계와, 상기 단계로부터 상기 터널산화막 및 폴리실리콘층을 패턴공정으로 패터닝하는 단계와, 상기 단계로부터 상기 실리콘기판상에 하부산화막을 형성한 후 그 위에 질화막을 형성하고, 그 위에 제 1상부산호막을 형성하는 단계와, 상기 단계로부터 상기 유전체막상에 희생 폴리실리콘층을 형성하는 단계와, 상기 단계로부터 고전압 트랜지스터영역을 오픈한 후 상기 희생 폴리실리콘층 및 유전체막을 제거하는 단계와, 상기 단계로부터 상기 실리콘기판의 전체 상부면에 고전압 게이트 산화막을 형성한 후 고전압 트랜지스터 영역상에 감광막을 형성하는 단계와, 상기 단계로부터 상기 감광막을 마스크로 이용하여 상기 희생 폴리실리콘층 및 고전압 게이트산화막을 프리 세정공정으로 제거한 후 상기 감광막을 제거하는 단계와, 상기 단계로부터 상기 실리콘기판의 전체 상부면에 저전압 게이트 산화막 및 제2상부산화막을 형성한 후 콘트롤게이트를 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 제조방법.A method of manufacturing a semiconductor device, comprising the steps of: forming a tunnel oxide film and a polysilicon layer on a silicon substrate on which a field oxide film is formed; patterning the tunnel oxide film and the polysilicon layer by a pattern process from the step; Forming a lower oxide film on the silicon substrate and then forming a nitride film thereon, and forming a first upper coral film thereon; forming a sacrificial polysilicon layer on the dielectric film from the step; Removing the sacrificial polysilicon layer and the dielectric film after opening the high voltage transistor region, forming a high voltage gate oxide film on the entire upper surface of the silicon substrate from the step, and then forming a photoresist film on the high voltage transistor region; The sacrificial polysilicon using the photosensitive film as a mask from the step Removing the photoresist layer after removing the cone layer and the high voltage gate oxide layer by a pre-cleaning process; forming a control gate after forming the low voltage gate oxide layer and the second upper oxide layer on the entire upper surface of the silicon substrate from the step; A method for manufacturing a semiconductor device, characterized in that made. 제1항에 있어서, 상기 하부산화막은 750 내지 850℃의 온도로 상기 폴리실리콘층을 산화시켜서 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the lower oxide layer is formed by oxidizing the polysilicon layer at a temperature of 750 to 850 ° C. 7. 제1항에 있어서, 상기 제1상부산화막은 상기 질화막을 산화시켜서 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the first upper oxide film is formed by oxidizing the nitride film. 제1항에 있어서, 상기 희생 폴리실리콘층은 SiH4및 Si2H6가스의 분위기하에서 450 내지 550℃의 온도로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the sacrificial polysilicon layer is formed at a temperature of 450 to 550 ° C. under an atmosphere of SiH 4 and Si 2 H 6 gas. 제1항 또는 제4항에 있어서, 상기 희생 폴리실리콘층은 고전압 게이트산화막의 두께의 1/2로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.5. The method of claim 1 or 4, wherein the sacrificial polysilicon layer is formed to one-half the thickness of the high voltage gate oxide film. 제1항에 있어서, 상기 제2상부산화막은 저전압 게이트산화막 형성시 질화막을 산화하여 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the second upper oxide layer is formed by oxidizing a nitride layer when the low voltage gate oxide layer is formed. 제1항에 있어서, 상기 프리 세정공정은 저전압 트랜지스터영역상의 저전압 게이트산화막이 제거될때 캐패시터영역상의 산화된 희생폴리실리콘층도 함께 제거하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the pre-cleaning process removes the oxidized sacrificial polysilicon layer on the capacitor region when the low voltage gate oxide layer on the low voltage transistor region is removed. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950065644A 1995-12-29 1995-12-29 Method of manufacturing semiconductor device KR100193892B1 (en)

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Application Number Priority Date Filing Date Title
KR1019950065644A KR100193892B1 (en) 1995-12-29 1995-12-29 Method of manufacturing semiconductor device

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Application Number Priority Date Filing Date Title
KR1019950065644A KR100193892B1 (en) 1995-12-29 1995-12-29 Method of manufacturing semiconductor device

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KR100193892B1 KR100193892B1 (en) 1999-06-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100538729B1 (en) * 2001-06-25 2005-12-26 가부시끼가이샤 도시바 A semiconductor device and manufacturing method thereof

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7927950B2 (en) 2002-05-07 2011-04-19 Samsung Electronics Co., Ltd. Method of fabricating trap type nonvolatile memory device
KR100437451B1 (en) * 2002-05-07 2004-06-23 삼성전자주식회사 Method Of Fabricating Trap-type Nonvolatile Memory Device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100538729B1 (en) * 2001-06-25 2005-12-26 가부시끼가이샤 도시바 A semiconductor device and manufacturing method thereof

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