KR930020717A - Spacer width adjustment method of MOS device - Google Patents
Spacer width adjustment method of MOS device Download PDFInfo
- Publication number
- KR930020717A KR930020717A KR1019920004219A KR920004219A KR930020717A KR 930020717 A KR930020717 A KR 930020717A KR 1019920004219 A KR1019920004219 A KR 1019920004219A KR 920004219 A KR920004219 A KR 920004219A KR 930020717 A KR930020717 A KR 930020717A
- Authority
- KR
- South Korea
- Prior art keywords
- spacer
- forming
- oxide film
- silicon substrate
- depositing
- Prior art date
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Abstract
MOS 소자의 소오스 및 드레인 영역을 형성할 때, BSG 또는 BPSG의 상압증착막을 사용하여 스페이서 마스크를 형성하고, 습식 식각을 이행한 후, O2어닐링 공정을 통하여 상압 증착막을 플로우 시킴으로, 소정의 스페이서폭을 얻을 수 있으며, 또한 실리콘기판 상부에 산화막을 형성시킴으로 실리콘 기판을 이온 주입에 의한 손상으로부터 보호할 수 있다.When forming the source and drain regions of the MOS device, a spacer mask is formed using an atmospheric pressure deposition film of BSG or BPSG, a wet etching is performed, and the atmospheric pressure deposition film is flowed through an O 2 annealing process, thereby providing a predetermined spacer width. By forming an oxide film on the silicon substrate, the silicon substrate can be protected from damage by ion implantation.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 본 발명의 실리콘 기판 상부의 게이트 산화막 상부에 폴리 실리콘을 증착시킨 후 포토레지스터 패턴을 형성시켜 식각공정을 이행하고, 그 상부에 섀도우 산화막을 형성시키고, 실리콘 기판내에 LDD영역을 형성시키는 공정을 나타내는 반도체 소자의 단면도이다.1 is a process of depositing polysilicon on a gate oxide film on a silicon substrate of the present invention, forming a photoresist pattern to perform an etching process, forming a shadow oxide film on the silicon substrate, and forming an LDD region in the silicon substrate. It is sectional drawing of the semiconductor element which shows.
제2도는 제1도의 공정 후, 상기 섀도우 산화막 상부에 상압 증착막을 형성시키는 공정을 나타내는 반도체 소자의 단면도이다.FIG. 2 is a cross-sectional view of a semiconductor device illustrating a process of forming an atmospheric vapor deposition film on the shadow oxide film after the process of FIG. 1.
제3도는 상기 상압 증착막 상부에 포토레지스터 층을 도포하는 공정을 나타내는 반도체 소자의 단면도이다.3 is a cross-sectional view of a semiconductor device illustrating a process of applying a photoresist layer on the atmospheric pressure deposition film.
제4도는 상기 포토레지스터 층을 이용하여 스페이서 마스크를 형성하는 공정을 나타내는 반도체 소자의 단면도이다.4 is a cross-sectional view of a semiconductor device illustrating a process of forming a spacer mask using the photoresist layer.
제5도는 상기 스페이서 마스크를 이용하여 식각공정을 이행한 후 스페이서 패턴을 형성하는 공정을 나타내는 반도체 소자의 단면도이다.5 is a cross-sectional view of a semiconductor device illustrating a process of forming a spacer pattern after performing an etching process using the spacer mask.
제6도는 상기 스페이서 패턴 상부에 잔존하는 포토레지스터를 제거한 후 어닐링(annealing)을 이행하여 소정의 폭을 가진 스페이서를 형성하는 반도체 소자의단면도이다.FIG. 6 is a cross-sectional view of a semiconductor device in which a photoresist remaining on the spacer pattern is removed and then annealed to form a spacer having a predetermined width.
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920004219A KR930020717A (en) | 1992-03-14 | 1992-03-14 | Spacer width adjustment method of MOS device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920004219A KR930020717A (en) | 1992-03-14 | 1992-03-14 | Spacer width adjustment method of MOS device |
Publications (1)
Publication Number | Publication Date |
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KR930020717A true KR930020717A (en) | 1993-10-20 |
Family
ID=67257294
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1019920004219A KR930020717A (en) | 1992-03-14 | 1992-03-14 | Spacer width adjustment method of MOS device |
Country Status (1)
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KR (1) | KR930020717A (en) |
-
1992
- 1992-03-14 KR KR1019920004219A patent/KR930020717A/en not_active Application Discontinuation
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