KR970030815A - Capacitor Manufacturing Method of Semiconductor Device - Google Patents

Capacitor Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR970030815A
KR970030815A KR1019950039166A KR19950039166A KR970030815A KR 970030815 A KR970030815 A KR 970030815A KR 1019950039166 A KR1019950039166 A KR 1019950039166A KR 19950039166 A KR19950039166 A KR 19950039166A KR 970030815 A KR970030815 A KR 970030815A
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KR
South Korea
Prior art keywords
forming
semiconductor device
capacitor
amorphous silicon
manufacturing
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Application number
KR1019950039166A
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Korean (ko)
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KR100200298B1 (en
Inventor
임찬
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김주용
현대전자산업주식회사
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Priority to KR1019950039166A priority Critical patent/KR100200298B1/en
Publication of KR970030815A publication Critical patent/KR970030815A/en
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Publication of KR100200298B1 publication Critical patent/KR100200298B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 반도체 소자의 캐피시터 제조 방법에 관한 것으로, 본 발명은 반도체 기억소자인 디램에서 단위면적당 캐패시터의 용량을 증대시키기 위하여, 저온에서 텅스텐실사이드의 약간량을 비정질실리콘의 상부에 분사하고, 열처리하여 반구형 실리콘 전극을 형성하므로써, 저장전극의 표면적을 증대시킨다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device. The present invention provides a method of manufacturing a semiconductor memory device, in which a small amount of tungsten silicide is injected onto the amorphous silicon at low temperature and heat treated to increase the capacity of the capacitor per unit area. By forming a hemispherical silicon electrode, the surface area of the storage electrode is increased.

Description

반도체 소자의 캐패시터 제조방법Capacitor Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2a도 내지 제2d도는 본 발명의 실시예에 의한 반도체소자의 캐패시터 제조 방법을 도시한 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device in accordance with an embodiment of the present invention.

Claims (11)

실리콘기판에 소자분리산화막과, 게이트산화막, 워드라인, 소오스／드레인이 구비되는 모스전계효과트랜지스터를 형성하고, 전체 구조의 상부에 평탄화용 절연층을 형성하는 단계와, 상기 소오스／드레인이 노출되는 콘택홀을 형성하는 단계와, 그 상부에 비정질실리콘층을 형성하는 단계와, 상기 비정질실리콘층 표면에 형성된 자연산화막을 제거하는 단계와, 상기 비정질실리콘층 표면에 텅스텐실리사이드 핵을 형성하는 단계와, 열처리공정으로 표면이 반구형인 저장전극을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.Forming a MOS field effect transistor including a device isolation oxide film, a gate oxide film, a word line, and a source / drain on a silicon substrate, and forming a planarization insulating layer over the entire structure, and exposing the source / drain. Forming a contact hole, forming an amorphous silicon layer thereon, removing a natural oxide film formed on the surface of the amorphous silicon layer, and forming a tungsten silicide nucleus on the surface of the amorphous silicon layer; A method of manufacturing a capacitor of a semiconductor device comprising the step of forming a storage electrode having a hemispherical surface in the heat treatment process. 제1항에 있어서, 상기 비정질실리콘층에 1×1017／㎠ 내지 2×1021／㎠ 정도의 불순물이 도프된 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The method of claim 1, wherein impurities of about 1 × 10 17 / cm 2 to about 2 × 10 21 / cm 2 are doped into the amorphous silicon layer. 제1항에 있어서, 상기 비정질실리콘층이 450 내지 550℃의 온도에서 SiH4, 또는 Si2H6를 사용하여 형성되는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The method of claim 1, wherein the amorphous silicon layer is formed using SiH 4 or Si 2 H 6 at a temperature of 450 to 550 ℃. 제1항에 있어서, 상기 자연산화막을 제거할 때, 불화수소로 습식식각하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The method of claim 1, wherein the removal of the natural oxide film is performed by wet etching with hydrogen fluoride. 제1항에 있어서, 상기 자연산화막을 제거할 때, 불화수소, 탈이온수 및 오존을 혼합한 기상상태의 물질을 이용하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The method of manufacturing a capacitor of a semiconductor device according to claim 1, wherein when removing said natural oxide film, a substance in a gaseous state in which hydrogen fluoride, deionized water and ozone are mixed is used. 제1항에 있어서, 상기 텅스텐 실리사이드 핵이 530 내지 560℃의 온도와, 1 Torr 이하의 압력에서 상기 비정질 실리콘층의 표면에 SiH2Cl2와 WF6의 혼합가스를 분사하여 형성되는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The method of claim 1, wherein the tungsten silicide core is formed by injecting a mixed gas of SiH 2 Cl 2 and WF 6 to the surface of the amorphous silicon layer at a temperature of 530 to 560 ℃ and a pressure of 1 Torr or less. A method for producing a capacitor of a semiconductor device. 제1항에 있어서, 상기 텅스텐 실리사이드 핵이 450℃ 이상의 온도와, 1 Torr이하의 압력에서 상기 비정질실리콘층의 표면에 SiH4와 WF6의 혼합가스를 분사하여 형성되는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The semiconductor device of claim 1, wherein the tungsten silicide nucleus is formed by spraying a mixed gas of SiH 4 and WF 6 on the surface of the amorphous silicon layer at a temperature of 450 ° C. or higher and a pressure of 1 Torr or less. Capacitor Manufacturing Method. 제1항에 있어서, 상기 텅스텐 실리사이드 핵의 텅스텐, 실리콘의 성분비는 1:1.5 내지 2.5인 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The method of manufacturing a capacitor of a semiconductor device according to claim 1, wherein the component ratio of tungsten and silicon in said tungsten silicide nucleus is 1: 1.5 to 2.5. 제1항에 있어서, 상기 저장전극을 형성하는 열처리공정이 565℃ 이상의 온도에서 진행되는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The method of claim 1, wherein the heat treatment process for forming the storage electrode is performed at a temperature of 565 ° C. or higher. 제1항에 있어서, 상기 저장전극을 형성하는 열처리공정을 할 때, 질소, 수소, 아르곤의 기체를 전체표면의 상부에 흘려주면서 튜브 내의 압력을 수백 mTorr 이하로 하여 진행하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The semiconductor device according to claim 1, wherein in the heat treatment process for forming the storage electrode, the pressure in the tube is advanced to several hundred mTorr or less while flowing nitrogen, hydrogen, and argon gas over the entire surface. Of capacitor manufacturing method. 제1항에 있어서, 상기 저장전극을 형성하는 열처리공정을 할 때, 기체를 흘려 주지않고, 튜브내의 압력을 수십 mTorr로 하여 진행하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The method of manufacturing a capacitor of a semiconductor device according to claim 1, wherein in the heat treatment step of forming the storage electrode, the pressure in the tube is set to several tens of mTorr without flowing gas. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950039166A 1995-11-01 1995-11-01 Capacitor device fabrication method of semiconductor KR100200298B1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100485113B1 (en) * 2000-07-28 2005-04-25 엔이씨 일렉트로닉스 가부시키가이샤 Capacitor electrode having uneven surface formed by using hemispherical grained silicon
KR100505413B1 (en) * 2002-06-28 2005-08-04 주식회사 하이닉스반도체 Method for manufactruing capacitor in semiconductor device
KR100694997B1 (en) * 2000-11-16 2007-03-14 주식회사 하이닉스반도체 method for forming capacitor semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100485113B1 (en) * 2000-07-28 2005-04-25 엔이씨 일렉트로닉스 가부시키가이샤 Capacitor electrode having uneven surface formed by using hemispherical grained silicon
KR100694997B1 (en) * 2000-11-16 2007-03-14 주식회사 하이닉스반도체 method for forming capacitor semiconductor device
KR100505413B1 (en) * 2002-06-28 2005-08-04 주식회사 하이닉스반도체 Method for manufactruing capacitor in semiconductor device

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