KR930014951A - Contact Forming Method for Highly Integrated Devices - Google Patents

Contact Forming Method for Highly Integrated Devices Download PDF

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Publication number
KR930014951A
KR930014951A KR1019910025621A KR910025621A KR930014951A KR 930014951 A KR930014951 A KR 930014951A KR 1019910025621 A KR1019910025621 A KR 1019910025621A KR 910025621 A KR910025621 A KR 910025621A KR 930014951 A KR930014951 A KR 930014951A
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KR
South Korea
Prior art keywords
layer
insulating layer
forming
pattern
polysilicon
Prior art date
Application number
KR1019910025621A
Other languages
Korean (ko)
Other versions
KR950013385B1 (en
Inventor
박철수
박재범
Original Assignee
정몽헌
현대전자산업 주식회사
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Publication date
Application filed by 정몽헌, 현대전자산업 주식회사 filed Critical 정몽헌
Priority to KR1019910025621A priority Critical patent/KR950013385B1/en
Priority to US07/989,196 priority patent/US5296400A/en
Priority to JP4333052A priority patent/JPH07105442B2/en
Publication of KR930014951A publication Critical patent/KR930014951A/en
Application granted granted Critical
Publication of KR950013385B1 publication Critical patent/KR950013385B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음No content

Description

고집적 소자용 콘택형성방법Contact Forming Method for Highly Integrated Devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 1 도 내지 제 6 도는 본 발명의 콘택형성방법을 적용하는 DRAM셀을 제조하는 단계를 도시한 단면도.1 to 6 are cross-sectional views showing steps of manufacturing a DRAM cell to which the contact forming method of the present invention is applied.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 기판 2A 및 2B : 소오스 및 드레인1: substrate 2A and 2B: source and drain

3 : 소자분리 산화막 4 : 게이트 산화막3: device isolation oxide film 4: gate oxide film

5 : 게이트전극 6 : 게이트전극 마스크 옥사이드5: gate electrode 6: gate electrode mask oxide

7 : 제 1 절연층 7A : 제 1 절연층 스페이서7: first insulating layer 7A: first insulating layer spacer

8 : 폴리이미드 9 : 제 2 절연층8: polyimide 9: second insulating layer

10 : 폴리실리콘층 10A : 폴리실리콘 패드10: polysilicon layer 10A: polysilicon pad

12A : 비트라인 13 : 제 3 절연층12A: bit line 13: third insulating layer

14 : 제 4 절연층 15 : 전하저장 전극용 도전층14 fourth insulating layer 15 conductive layer for charge storage electrode

Claims (5)

반도체 소자 제조방법에 있어서, 실리콘 기판 상부에 소자분리 산화막, 게이트전극, 소오스 및 드레인으로 구비되는 MOSFET를 형성하고, 전체구조 상부 제 1 절연층을 형성하는 단계와, 상기 옥사이드 상부에 감광성 폴리이미드를 평탄하게 도포한 다음, 노광 및 형성공정으로 소오스 및 드레인의 콘택영역 상부에만 폴리이미드 패턴을 형성하는 단계와, 상기 폴리이미드 패턴을 포함하는 전체구조 상부에 제 2 절연층을 두껍게 형성한 후 에치백공정으로 상기 폴리이미드 패턴 최상부면이 노출되기까지 제거하여 제 2 절연층 패턴을 평탄하게 형성하는 단계와, 노출된 폴리이미드 패턴을 플라즈마 식각으로 제거하고, 노출되는 하부의 제 1 절연층을 블렌켓 식각하여 하부의 콘택영역을 노출시키고 동시에 게이트전극 측벽에 스페이서를 형성하는 단계와, 전체구조 상부에 폴리실리층을 두껍게 증착하고 에치백 공정으로 상기 제 2 절연층 패턴 외상부까지 식각하여 하부드레인 및 소오스에 접속된 폴리실리콘 패드를 형성하는 단계와, 상기 폴리실리콘 패드를 포함한 전체구조 상부에 제 3 절연층을 도포하고 예정된 콘택영역의 제 3 절연층을 제거하여 폴리실리콘 패드를 노출시킨 다음, 도전층을 증착하는 단계로 이루어져 상부의 도전층을 폴리실리콘 패드를 통하여 소오스 또는 드레인에 콘택하는 것을 특징으로 하는 고집적 소자용 콘택형성방법.A method for manufacturing a semiconductor device, comprising: forming a MOSFET including a device isolation oxide film, a gate electrode, a source, and a drain on a silicon substrate, forming a first insulating layer on an entire structure, and photosensitive polyimide on the oxide After coating the film, the polyimide pattern is formed only on the contact regions of the source and the drain by the exposure and forming process, and the second insulation layer is thickly formed on the entire structure including the polyimide pattern. Forming a second insulating layer pattern by removing the top surface of the polyimide pattern until it is exposed, removing the exposed polyimide pattern by plasma etching, and blanketing the exposed first insulating layer. Etching to expose the lower contact region and simultaneously forming spacers on the sidewalls of the gate electrode; Depositing a thick polysilicon layer on top of the body structure and etching to the outer surface of the second insulating layer pattern by an etch back process to form a polysilicon pad connected to a lower drain and a source, and the entire structure including the polysilicon pad Applying a third insulating layer to the upper layer, removing the third insulating layer of the predetermined contact region to expose the polysilicon pads, and then depositing a conductive layer, thereby forming the upper conductive layer on the source or drain through the polysilicon pad. A contact forming method for a highly integrated device, characterized in that for contacting. 제 1 항에 있어서, 상기 제 1 절연층은 옥사이드층으로 형성하는 것을 특징으로 하는 고집적 소자용 콘택형성방법.The method of claim 1, wherein the first insulating layer is formed of an oxide layer. 제 1 항에 있어서, 상기 감광성 폴리이미드 대신에 포토레지스트를 형성하는 것을 특징으로 하는 고집적 소자용 콘택형성방법.The contact forming method of claim 1, wherein a photoresist is formed in place of the photosensitive polyimide. 제 1 항에 있어서, 상기 제 2 절연층은 LTO층, PECVD 옥사이드층, 오존 TEOS층, 오존 BPSG층, SOG층 또는 PETEOS층으로 형성하는 것을 특징으로 하는 고집적 소자용 콘택형성방법.The method of claim 1, wherein the second insulating layer is formed of an LTO layer, a PECVD oxide layer, an ozone TEOS layer, an ozone BPSG layer, an SOG layer, or a PETEOS layer. 제 1 항에 있어서, 상기 폴리실리콘 패드 상부면에 콘택되는 도전층은 비트라인 또는 전하저장전극용 도전층으로 형성하는 것을 특징으로 하는 고집적 소자용 콘택형성방법.The method of claim 1, wherein the conductive layer contacting the upper surface of the polysilicon pad is formed as a conductive layer for a bit line or a charge storage electrode. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910025621A 1991-12-14 1991-12-31 Contact formation method for lsi device KR950013385B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019910025621A KR950013385B1 (en) 1991-12-31 1991-12-31 Contact formation method for lsi device
US07/989,196 US5296400A (en) 1991-12-14 1992-12-11 Method of manufacturing a contact of a highly integrated semiconductor device
JP4333052A JPH07105442B2 (en) 1991-12-14 1992-12-14 Highly integrated semiconductor device contact manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910025621A KR950013385B1 (en) 1991-12-31 1991-12-31 Contact formation method for lsi device

Publications (2)

Publication Number Publication Date
KR930014951A true KR930014951A (en) 1993-07-23
KR950013385B1 KR950013385B1 (en) 1995-11-02

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100367402B1 (en) * 1998-12-31 2003-04-21 주식회사 하이닉스반도체 Data transmission line formation method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100367402B1 (en) * 1998-12-31 2003-04-21 주식회사 하이닉스반도체 Data transmission line formation method of semiconductor device

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Publication number Publication date
KR950013385B1 (en) 1995-11-02

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