KR100255168B1 - Method of cleaning a contact hole in a semiconductor device - Google Patents

Method of cleaning a contact hole in a semiconductor device Download PDF

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KR100255168B1
KR100255168B1 KR1019970026316A KR19970026316A KR100255168B1 KR 100255168 B1 KR100255168 B1 KR 100255168B1 KR 1019970026316 A KR1019970026316 A KR 1019970026316A KR 19970026316 A KR19970026316 A KR 19970026316A KR 100255168 B1 KR100255168 B1 KR 100255168B1
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contact hole
hydrofluoric acid
cleaning
oxide film
contact
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KR1019970026316A
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KR19990002645A (en
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임성수
김학묵
이주영
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김영환
현대전자산업주식회사
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/0206Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02043Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052Wet cleaning only

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for cleaning a contact hole of a semiconductor device is provided to remove a natural oxide layer from a contact surface within a short time after removing an organic material and metallic impurity and minimize a damage of a chemical vapor deposition oxide film of a sidewall. CONSTITUTION: A gate(12) is formed on a silicon substrate(11). A gate spacer oxide layer(14) for forming an LDD(Lightly Doped Drain) structure(13) is formed thereon. A planarization process is performed by using an inter-poly oxide film and a BPSG layer(15). A contact hole is formed by a contact mask and an etching process. The ozonized water is formed by implanting ozone gas into pure water with a temperature of 5 to 10 degrees centigrade. An organic material and metallic impurities are removed from a contact hole by utilizing an overflow method using the ozonized water. A natural oxide layer is removed from a surface of a contact by utilizing the overflow method using low density fluoric acid chemicals. A cleaning process is performed by using pure water. A dry process is performed.

Description

반도체 소자의 콘택 홀 세정 방법{Method of cleaning a contact hole in a semiconductor device}Method of cleaning a contact hole in a semiconductor device

본 발명은 모든 반도체 소자에 적용할 수 있는 세정(cleaning) 공정에 관한 것으로, 특히 반도체 소자의 콘택 홀(contact hole) 세정 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cleaning process applicable to all semiconductor devices, and more particularly to a method of cleaning contact holes in semiconductor devices.

종래의 반도체 소자 제조 공정에 있어서 소자가 고집적화 된 256M 급에서는 소오스(source) 및 드래인(drain)이 0.08 ㎛의 얕은 접합(shallow junction) 으로 형성되며, 최종 콘택 홀 크기(final contact hole size)는 0.15 ㎛ 이하이다. 또한 1G 급의 소자에서는 0.06 ㎛, 0.1 ㎛ 정도의 매우 얕은 접합(shallow junction) 및 아주 좁은 콘택 홀 (contact hole) 형성이 요구된다. 이렇게 접합깊이(junction depth)가 얕아짐에 따라 콘택 홀 크기(contact hole size)가 급격하게 작아지므로 콘택(contact) 저항이 크게 증가되는 요인이 된다. 또한 비트 라인(bit line) 및 저장 노드(storage node)를 형성시키기 전에, 일반적으로 게이트 전극용 제 1 폴리실리콘층과 비트라인용 제 2 폴리실리콘층, 게이트 전극용 제 1 폴리실리콘층과 전하 저장 전극용 제 3 폴리실리콘층, 그리고 비트라인용 제 2 폴리실리콘층과 전하 저장 전극용 제 3 폴리실리콘층의 전기적인 절연파괴를 방지하기 위하여 화학기상증착 산화막(cvd oxide film)을 이용한 스페이서 산화막(spacer oxide film)을 형성시킨다. 그런데 현재 불산(HF) 이나, BOE(Buffered Oxide Exchant) 용액 등을 이용한 습식 세정(wet cleaning)과정은 자연산화막 뿐만 아니라 위와 같은 콘택(contact) 측벽의 화학기상증착 산화막(cvd oxide film)도 같이 제거되어, 게이트 전극용 제 1 폴리실리콘층과 비트라인용 제 2 폴리실리콘층, 게이트 전극용 제 1 폴리실리콘층과 전하 저장 전극용 제 3 폴리실리콘층, 그리고 비트라인용 제 2 폴리실리콘층과 전하 저장 전극용 제 3 폴리실리콘층의 전기적인 절연파괴로 소자의 수율향상 및 특성에 심각한 영향을 준다. 따라서 한편으로 콘택(contact)부위의 자연산화막 성장을 억제하기 위하여 증착튜브에 질소 정화통(N2purge box) 또는 로드 락 시스템(load lock system)을 부착하여 사용하기도하나 완전히 제어하지는 못한다. 그러므로 상기와 같은 차세대 초고집적 소자에서는 소스(source)/드레인(drain)층의 저항이 증가되고, 게이트 길이(gate length)가 아주 작을 경우 이들 저항이 트랜스 콘덕턴스(trance conductance) 특성 및 소자의 구동능력 저하를 초래하기 때문에 콘택(contact) 저항의 제어는 아주 중요한 문제이다.In the conventional semiconductor device manufacturing process, the source and the drain are formed with a shallow junction of 0.08 μm in the 256M class in which the device is highly integrated, and the final contact hole size is 0.15 micrometer or less. In addition, in the 1G class devices, very shallow junctions such as 0.06 μm and 0.1 μm and very narrow contact holes are required. As the junction depth becomes shallower, the contact hole size decreases drastically, which causes a large increase in contact resistance. Also, before forming the bit lines and storage nodes, the first polysilicon layer for the gate electrode and the second polysilicon layer for the bit line, the first polysilicon layer for the gate electrode and charge storage are generally used. In order to prevent electrical breakdown of the third polysilicon layer for the electrode, the second polysilicon layer for the bit line and the third polysilicon layer for the charge storage electrode, a spacer oxide film using a cvd oxide film ( spacer oxide film). However, the wet cleaning process using hydrofluoric acid (HF) or BOE (Buffered Oxide Exchant) solution removes not only the natural oxide layer but also the CVD oxide film on the contact sidewalls. The first polysilicon layer for the gate electrode and the second polysilicon layer for the bit line, the first polysilicon layer for the gate electrode and the third polysilicon layer for the charge storage electrode, and the second polysilicon layer for the bit line and the charge Electrical breakdown of the third polysilicon layer for storage electrodes has a significant effect on the yield improvement and characteristics of the device. Therefore, in order to suppress the growth of the native oxide film of the contact (contact), a nitrogen purge (N 2 purge box) or a load lock system (attach) is attached to the deposition tube, but not completely controlled. Therefore, in the next generation of ultra-high density devices, the resistance of the source / drain layer is increased, and when the gate length is very small, these resistances are used for the conductance characteristics and driving of the device. Control of contact resistance is a very important issue because it leads to a reduction in capability.

현재 반도체 제조 공정에서 사용중인 기술은, 자연산화막, 산화막, 오염물질 즉 유기물과 금속성 잔류 불순물과 같은 무기물을 제거하기 위한 세정 방법으로 여러 가지 세정 방법을 조합해서 사용한다. 1차로 미립자(particle) 및 유기물을 제거하기 위하여 황산(H2SO4)과 과산화수소수(H2O2)를 혼합한 황산용액(piranha)이나, 암모니아수(NH4OH)와 과산화수소수(H2O2) 및 순수(deionized water)를 혼합한 암모니아용액(SC1)을 사용하여 세정한 후, QDR(Quick Dump Rinse)방법으로 씻어낸다. 2차로 불산(HF)이나 BOE(Buffered Oxide Exchant) 용액으로 산화막 제거를 위한 세정을 한 후 순수(deionized water)를 사용하여 오버플로우(overflow) 방식으로 씻어낸다. 3차로는 무기물 제거를 위하여 염산(HCl)과 과산화수소수(H2O2) 및 순수(deionized water)을 혼합한 염산 용액을 사용하여 세정한다. 근래에는 화학약품의 순도가 향상되어 3차 세정은 하지않는 추세이다. 그리고나서 건조기로 웨이퍼를 건조한다. 이러한 세정 방법은 많은 양의 화학약품을 소비하고 세정 시간이 길어지며 웨이퍼 크기가 커짐에 따라 세정 장비 자체의 크기도 증가되어 청정실(clean room)의 많은 면적을 차지함으로써 생산성을 저하시켜 왔다. 또한 상기의 기존 콘택 홀(contact hole) 세정 공정은 130 ℃의 고온 황산용액(piranha)으로 콘택(contact) 표면에 존재하는 유기물과 무기물을 제거하기 때문에 그동안 화학물질 속에서 자연산화막이 10 Å 정도나 자라게 되어, 후속 자연산화막 제거 공정인 불산(HF) 또는 BOE(Buffered Oxide Exchant) 용액에서의 담금시간(dip time)이 증가하게된다. 그러므로 인해 콘택 홀(contact hole) 측벽에 있는 전극간의 절연막인 화학기상증착 산화막(cvd oxide film)의 손실이 심해져서 게이트 전극용 제 1 폴리실리콘층과 비트라인용 제 2 폴리실리콘층, 게이트 전극용 제 1 폴리실리콘층과 전하 저장 전극용 제 3 폴리실리콘층, 그리고 비트라인용 제 2 폴리실리콘층과 전하 저장 전극용 제 3 폴리실리콘층의 전기적인 절연파괴가 유발되기도 하며 따라서 소자의 특성에 영향을 주기도 한다.The technology currently used in the semiconductor manufacturing process uses a combination of various cleaning methods as a cleaning method for removing natural oxides, oxides, contaminants, that is, inorganic matters such as organic substances and metallic residual impurities. Primary sulfuric acid solution (piranha) mixed with sulfuric acid (H 2 SO 4 ) and hydrogen peroxide (H 2 O 2 ) to remove particulates and organics, or ammonia water (NH 4 OH) and hydrogen peroxide (H 2) After washing with ammonia solution (SC1) mixed with O 2 ) and deionized water, it is washed with QDR (Quick Dump Rinse) method. Secondly, the oxide film is washed with hydrofluoric acid (HF) or BOE (Buffered Oxide Exchant) solution to remove the oxide film, and then washed with overflow using deionized water. In order to remove the inorganic material, the third step is washed with a hydrochloric acid solution in which hydrochloric acid (HCl), hydrogen peroxide solution (H 2 O 2 ), and deionized water are mixed. In recent years, the purity of chemicals has improved, and the third cleaning process is not performed. The wafer is then dried in a dryer. Such cleaning methods have consumed a large amount of chemicals, have a long cleaning time, and as the size of the wafer increases, the size of the cleaning equipment itself increases, thereby decreasing productivity by occupying a large area of a clean room. In addition, the conventional contact hole cleaning process removes organic and inorganic substances on the contact surface with a high temperature sulfuric acid solution (piranha) at 130 ° C. As it grows, the dip time in the hydrofluoric acid (HF) or BOE (Buffered Oxide Exchant) solution, which is a subsequent natural oxide removal process, is increased. Therefore, the loss of the cvd oxide film, which is an insulating film between the electrodes on the sidewalls of the contact hole, is increased, so that the first polysilicon layer for the gate electrode and the second polysilicon layer for the bit line and the gate electrode Electrical breakdown of the first polysilicon layer, the third polysilicon layer for the charge storage electrode, and the second polysilicon layer for the bit line and the third polysilicon layer for the charge storage electrode is caused, thus affecting the characteristics of the device. Also give.

본 발명은, 유기물과 금속적 불순물(metallic impurity)을 제거한 후 콘택(contact) 표면에 화학적으로 형성된 자연산화막을 짧은 시간내에 완전히 제거시키면서, 측벽의 화학기상증착 산화막(chemical vapor deposition oxide film)의 손실을 최소화시키는데 그 목적이 있다.The present invention provides a loss of a chemical vapor deposition oxide film on a sidewall while completely removing a natural oxide film chemically formed on a contact surface in a short time after removing organic matter and metallic impurity. The purpose is to minimize this.

상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 콘택 홀 세정 방법은, 순수(deionized water)에 오존 가스를 주입한 저온 오존수를 이용한 세정을 통하여 유기물과 금속적 불순물을 오버플로우 방식으로 제거하는 단계와, 저농도의 불산계열 화학약품으로 콘택(contact) 표면의 자연산화막을 오버플로우 방식으로 제거시키는 단계와, 순수를 이용해 세정하는 단계와, 건조하는 단계로 이루어진 것을 특징으로 한다.The contact hole cleaning method of the semiconductor device according to the present invention for achieving the above object is to remove the organic matter and metallic impurities in an overflow method through the cleaning using cold ozone water injecting ozone gas into the deionized water. And a step of removing the natural oxide film on the contact surface in an overflow method with a low concentration of hydrofluoric acid-based chemical, washing with pure water, and drying.

도 1 및 도 2는 본 발명에 따른 콘택 홀 세정 방법을 설명하기 위한 단면도.1 and 2 are cross-sectional views for explaining a contact hole cleaning method according to the present invention.

<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>

11 및 21 : 실리콘 기판 12 및 22 : 게이트(gate) 층11 and 21: silicon substrate 12 and 22: gate layer

13 및 23 : LDD 구조층13 and 23: LDD structure layer

14 및 24 : 게이트 스페이서 산화층(gate spacer oxide)14 and 24: gate spacer oxide

15 및 25 : 인터 폴리 산화막(IPO) 및 BPSG 층15 and 25: interpoly oxide (IPO) and BPSG layers

26 : 비트 라인용 제 2 폴리실리콘층 27 : 텅스텐 실리사이드(W-Si)층26 second polysilicon layer for bit line 27 tungsten silicide (W-Si) layer

28 : 전하 저장 전극용 제 3 폴리실리콘층28: third polysilicon layer for charge storage electrode

첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.The present invention will be described in detail with reference to the accompanying drawings.

도 1은 본 발명에 의한 방법으로 세정하는 공정 설명하기 위해 콘택 홀 형성 과정을 도시한 소자의 단면도이다. 먼저 실리콘 기판(11)에 게이트(12)를 형성한 후 LDD구조(13)를 형성하기 위하여 게이트 스페이서 산화(gate spacer oxide)(14)층을 형성하고, 인터-폴리 산화막(inter poly oxide film) 및 BPSG 층(15)을 이용하여 평탄화 공정을 실시한다. 다음으로 콘택 마스크(contact mask) 및 식각(etch) 공정으로 콘택 홀(contact hole)을 형성한다.1 is a cross-sectional view of a device illustrating a process of forming a contact hole for explaining a process of cleaning by the method according to the present invention. First, a gate 12 is formed on the silicon substrate 11, and then a gate spacer oxide 14 layer is formed to form the LDD structure 13, and an inter poly oxide film is formed. And a planarization process using the BPSG layer 15. Next, contact holes are formed by a contact mask and an etching process.

먼저 미립자(particle), 유기물 및 무기물을 제거하기 위해 5 ℃ ∼ 10 ℃의 순수(deionized water)에 오존 가스를 주입한 저온 오존수(chilled ozone water)를 이용하여 오버플로우(overflow) 방식으로 세정한다. 이 방법은 종래의 130 ℃ 정도의 고온 황산용액(piranha) 또는 암모니아수 용액(NH4OH)를 사용한 세정 공정보다 저온에서 진행되기 때문에 용액속에서 성장되는 자연산화막의 두께를 4 Å 이내로 제한 할 수 있다. 따라서 후속 공정인 자연산화막 제거 단계에서 불산계열 용액을 저농도로 희석시켜도 사용이 가능하다. 불산(HF)용액의 경우 증류수(H2O)와 불산(HF)의 혼합 비율을 100 ∼ 500 : 1로 희석하고, BOE(Buffered Oxide Exchant) 용액의 경우는 NH4F와 불산(HF)의 혼합 비율을 100 ∼ 500 : 1로 희석하여 사용한다. 본 발명의 이러한 공정에서는 담금시간(dip time)을 짧게하여도 콘택 홀(contact hole) 표면에 형성된 미립자, 유기물 및 무기물, 자연산화막을 완전히 제거시키면서, 콘택 홀(contact hole) 측벽의 화학기상증착 산화막(chemical vapor deposition oxide film) 손실을 최소화 시킬 수 있다. 이후 순수에 의한 오버플로우 방식의 세정 공정과 건조 공정이 실시된다.First, in order to remove particles, organic matter, and inorganic matter, it is washed by an overflow method using chilled ozone water in which ozone gas is injected into deionized water of 5 ° C to 10 ° C. Since this method is performed at a lower temperature than the conventional washing process using a high temperature sulfuric acid solution (piranha) or ammonia water solution (NH 4 OH) of about 130 ℃, the thickness of the natural oxide film grown in the solution can be limited to within 4 kPa. . Therefore, it is possible to use the hydrofluoric acid-based solution in low concentration in the subsequent step of removing the natural oxide film. In the case of hydrofluoric acid (HF) solution, the mixing ratio of distilled water (H 2 O) and hydrofluoric acid (HF) is diluted to 100 to 500: 1, and in the case of BOE (Buffered Oxide Exchant) solution, NH 4 F and hydrofluoric acid (HF) The mixture ratio is diluted to 100-500: 1 and used. In this process of the present invention, even when the dip time is short, the chemical vapor deposition oxide film on the sidewall of the contact hole is completely removed while completely removing the fine particles, organic and inorganic materials, and the natural oxide film formed on the contact hole surface. (chemical vapor deposition oxide film) losses can be minimized. Thereafter, an overflow cleaning process and a drying process using pure water are performed.

도 2는 본 발명에 의한 방법으로 세정한 이후의 단계를 도시한 소자의 단면도로써 순차적으로 형성된 각 층간에, 즉 게이트 전극용 제 1 폴리실리콘층(22)과 비트라인용 제 2 폴리실리콘층(26), 게이트 전극용 제 1 폴리실리콘층(22)과 전하 저장 전극용 제 3 폴리실리콘층(28)의 전기적 절연 특성이 파괴되지 않은 안정된 소자의 단면을 보여주고 있다.FIG. 2 is a cross-sectional view of a device showing the steps after cleaning by the method according to the present invention. 26) shows a cross section of a stable device in which the electrical insulation properties of the first polysilicon layer 22 for the gate electrode and the third polysilicon layer 28 for the charge storage electrode are not destroyed.

상술한 바와 같이 본 발명에 의하면, 상기와 같은 공정을 이용한 콘택(contact) 세정 공정을 실시할 경우 콘택(contact) 부분에 형성된 자연산화막이 완전히 제거되고, 특히 저농도 불산계의 화학약픔을 사용하기 때문에 균질화(uniformity) 특성이 개선되며, 측벽에 형성되어 있는 스페이서 산화막(spacer oxide film)의 손실을 최소화 시켜주므로써 콘택(contact) 저항을 최소한으로 제어할 수 있어 소자 특성을 크게 향상시킬 수 있다. 또한 황산(H2SO4)과 과산화수소수(H2O2)와 같은 화학약품의 대용으로 순수한 물과 오존 가스를 사용하기 때문에 화학약품 소비의 감소 및 공정의 단순화로 세정 시간의 단축 및 장비 크기의 소형화가 가능하다.As described above, according to the present invention, when the contact cleaning process using the above process is performed, the natural oxide film formed on the contact portion is completely removed, and in particular, a chemical agent of low concentration hydrofluoric acid is used. Uniformity is improved and contact resistance can be minimized by minimizing the loss of the spacer oxide film formed on the sidewalls, thereby greatly improving device characteristics. In addition, pure water and ozone gas are used in place of chemicals such as sulfuric acid (H 2 SO 4 ) and hydrogen peroxide (H 2 O 2 ) to reduce chemical consumption and simplify the process to reduce cleaning time and equipment size. It is possible to miniaturize.

Claims (6)

5℃ 내지 10℃의 온도를 유지하는 순수에 오존 가스를 주입한 오존수를 이용한 세정을 통하여 콘택 홀내의 유기물과 금속적 불순물을 오버플로우 방식으로 제거하는 단계와,Removing organic matter and metallic impurities in the contact hole in an overflow manner by washing with ozone water in which ozone gas is injected into pure water maintaining a temperature of 5 ° C to 10 ° C, 저농도의 불산 계열 화학 약품으로 콘택 표면의 자연 산화막을 오버플로우 방식으로 제거시키는 단계와,Using a low concentration hydrofluoric acid chemical to remove the natural oxide film on the contact surface in an overflow manner; 순수를 이용한 세정 공정을 실시한 후 건조시키는 단계로 이루어진 것을 특징으로 하는 반도체 소자의 콘택 홀 세정 방법.A contact hole cleaning method for a semiconductor device, characterized in that the step of performing a cleaning process using pure water and then drying. 제 1 항에 있어서, 상기 오존수에 주입되는 오존 가스의 농도는 20ppm 내지 30ppm인 것을 특징으로 하는 반도체 소자의 콘택 홀 세정 방법.The method of claim 1, wherein the concentration of ozone gas injected into the ozone water is 20 ppm to 30 ppm. 제 1 항에 있어서, 상기 저온 오존수의 오버플로우비는 5LPM 내지 10LPM인 것을 특징으로 하는 반도체 소자의 콘택 홀 세정 방법.The method of claim 1, wherein the overflow ratio of the low temperature ozone water is 5LPM to 10LPM. 제 1 항에 있어서, 상기 저농도 불산계 용액은 증류수(H2O)와 불산(HF)을 100 내지 500 대 1로 혼합한 불산(HF) 용액인 것을 특징으로 하는 반도체 소자의 콘택 홀 세정 방법.The method of claim 1, wherein the low concentration hydrofluoric acid solution is a hydrofluoric acid (HF) solution in which distilled water (H 2 O) and hydrofluoric acid (HF) are mixed in an amount of 100 to 500 to 1. 제 1항에 있어서, 상기 저농도 불산계 용액은 NH4F와 불산(HF)을 100 내지 500 대 1로 혼합한 BOE 용액인 것을 특징으로 하는 반도체 소자의 콘택 홀 세정 방법.The method of claim 1, wherein the low concentration hydrofluoric acid-based solution is a BOE solution in which NH 4 F and hydrofluoric acid (HF) are mixed at a ratio of 100 to 500 to 1. 제 1 항에 있어서, 상기 자연 산화막은 상기 저농도 불산계 화학 약품을 20℃ 내지 30℃의 범위에서 5LPM 내지 10LPM의 오버플로우비로 제어하여 제거되는 것을 특징으로 하는 반도체 소자의 콘택 홀 세정 방법.The method of claim 1, wherein the native oxide film is removed by controlling the low concentration hydrofluoric acid chemical at an overflow ratio of 5 LPM to 10 LPM in a range of 20 ° C to 30 ° C.
KR1019970026316A 1997-06-20 1997-06-20 Method of cleaning a contact hole in a semiconductor device KR100255168B1 (en)

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KR100818089B1 (en) * 2006-08-30 2008-03-31 주식회사 하이닉스반도체 Method of manufacturing semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100866128B1 (en) 2002-12-21 2008-10-31 주식회사 하이닉스반도체 method for eliminating photoresist and slurry in storage node contact

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