KR100292116B1 - Method for forming isolation layer of semiconductor device - Google Patents

Method for forming isolation layer of semiconductor device Download PDF

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KR100292116B1
KR100292116B1 KR1019970082310A KR19970082310A KR100292116B1 KR 100292116 B1 KR100292116 B1 KR 100292116B1 KR 1019970082310 A KR1019970082310 A KR 1019970082310A KR 19970082310 A KR19970082310 A KR 19970082310A KR 100292116 B1 KR100292116 B1 KR 100292116B1
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insulating film
forming
film
semiconductor device
resultant
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KR1019970082310A
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Korean (ko)
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KR19990062005A (en
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오영균
양정일
진한호
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박종섭
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

PURPOSE: A method for forming an insulating layer of a semiconductor devices is provided to enhance an electron mobility of a gate electrode by improving a thickness uniformity of a gate oxide. CONSTITUTION: An insulating layer(20) having contact holes is formed on a silicon substrate(10) having transistors. A lower electrode(22) is formed to connect to source and drain regions(18) via the contact holes. After forming a first insulating layer(24) on the resultant structure by high temperature oxidation, a second insulating layer(24') is formed by wet-oxidation. After forming a nitride layer(26) on the resultant structure, a third and a fourth insulating layers(28,28') are formed by high temperature oxidation and by wet-oxidation, thereby forming dielectric layers of ONO(Oxide Nitride Oxide) structure. Then, an upper electrode(30) is formed on the dielectric layers of ONO structure.

Description

반도체 장치의 절연막 형성 방법{METHOD FOR FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE}METHODS FOR FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE

본 발명은 반도체 장치의 절연막 형성 방법에 관한 것으로서, 특히 반도체 장치의 고집적화에 따른 절연막 두께의 감소로 야기되는 소자의 전기적 특성 저하의 한계를 극복할 수 있는 반도체 장치의 절연막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an insulating film of a semiconductor device, and more particularly, to a method for forming an insulating film of a semiconductor device capable of overcoming the limitation of deterioration of electrical characteristics of a device caused by a decrease in the thickness of the insulating film due to high integration of the semiconductor device.

통상적으로 반도체 장치는 기억소자가 고집적화될수록 모스 트랜지스터의 전기적 특성에 큰 영향을 미치는 게이트 산화막의 두께 또한 감소하고 있다. 즉, 모스 트랜지스터는 원하는 전기적 특성을 얻기 위해 게이트 산화막의 두께가 균일해야하며 산화막과 기판의 경계면이 평탄해야 한다. 이러한 요인들이 충족되어야 하는 이유는 모스 트랜지스터의 반전층에서 발생하는 전자 이동도를 결정하는 캐리어 변환에 큰 영향을 끼치기 때문이다. 한편, 전자 이동도는 디바이스의 모델링과 디자인에 영향을 미치는 중요한 파라미터이다.In general, as the memory device becomes more integrated, the thickness of the gate oxide film, which greatly affects the electrical characteristics of the MOS transistor, is also reduced. That is, the MOS transistor needs to have a uniform thickness of the gate oxide film and a flat interface between the oxide film and the substrate in order to obtain desired electrical characteristics. These factors must be satisfied because they have a great influence on the carrier conversion which determines the electron mobility occurring in the inversion layer of the MOS transistor. On the other hand, electron mobility is an important parameter that affects the modeling and design of the device.

종래 기술에 의한 모스 트랜지스터의 제조 공정은 우선, 소자 분리 영역이 형성된 기판에 선 클리닝(cleaning) 공정을 실시하였다. 이때, 사용되는 용액은 HF+H2O 내지 NH4OH+H2O2+H2O 중에서 선택하였다. 그 다음 습식 산화 공정으로 800∼900℃, 1.0atm 반응 챔버내 압력에서 기판 전면에 50∼200Å의 두께를 가지는 게이트 산화막을 형성하였다. 그리고, 그 위에 폴리실리콘층을 형성하였다.In the manufacturing process of the MOS transistor by the prior art, the line cleaning process was first performed to the board | substrate with which the element isolation region was formed. In this case, the solution used was selected from HF + H 2 O to NH 4 OH + H 2 O 2 + H 2 O. Then, a gate oxide film having a thickness of 50 to 200 kPa was formed on the entire surface of the substrate at 800 to 900 ° C. and a pressure in a 1.0 atm reaction chamber by a wet oxidation process. And a polysilicon layer was formed on it.

상기와 같은 통상의 제조 공정에 의해 형성된 모스 트랜지스터는 소스 부위의 저전자장에서의 전자 이동도에 따라 트랜지스터의 속도가 변하였다. 그러므로, 종래 기술의 제조 공정으로 반도체 장치의 절연막을 제조할 경우 그 두께가 100Å까지는 영향이 작지만 그 이하에서는 소자의 전지적 특성에 악영향을 끼치게 되는 문제점이 있었다.In the MOS transistor formed by the conventional manufacturing process as described above, the speed of the transistor changed according to the electron mobility in the low field of the source region. Therefore, when the insulating film of the semiconductor device is manufactured by the manufacturing process of the prior art, the thickness is small up to 100 kPa, but below that there is a problem that adversely affects the battery characteristics of the device.

본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 반도체 장치의 고집적화에 따른 얇은 절연막 형성시 소자의 전지적 특성이 저하되는 것을 방지하는 반도체 장치의 절연막 형성 방법을 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method of forming an insulating film of a semiconductor device which prevents the battery characteristics of the device from deteriorating when a thin insulating film is formed due to high integration of the semiconductor device in order to solve the problems of the prior art.

도 1a 내지 도 1d는 본 발명의 일 실시예에 따른 반도체 장치의 절연막 형성 공정을 순차적으로 나타낸 공정 순서도.1A to 1D are process flowcharts sequentially illustrating an insulating film forming process of a semiconductor device according to an embodiment of the present invention.

도 2a 내지 도 2g는 본 발명의 다른 실시예에 따른 반도체 장치의 절연막 형성 공정을 순차적으로 나타낸 공정 순서도.2A to 2G are process flowcharts sequentially illustrating an insulating film forming process of a semiconductor device according to another embodiment of the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

10: 실리콘 기판 12: 소자 분리 영역10: silicon substrate 12: device isolation region

14: 제 1 절연막 14': 제 2 절연막14: first insulating film 14 ': second insulating film

16: 게이트 도전층 16': 게이트 전극16: gate conductive layer 16 ': gate electrode

18: 소스/드레인 접합층 20: 층간 절연막18: source / drain junction layer 20: interlayer insulating film

22: 하부 전극22: lower electrode

상기 목적을 달성하기 위하여 본 발명은 하부 구조물과 상부 구조물 사이를 층간 절연하기 위해 절연막을 형성함에 있어서, 하부 구조물 표면에 형성된 자연 산화막을 제거하는 단계; 상기 하부 구조물 표면에 고온 산화 공정으로 제 1 절연막을 형성하는 단계; 및 상기 제 1 절연막 위에 습식 산화 공정으로 제 1 절연막보다 두껍게 제 2 절연막을 형성하는 단계로 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention is to form an insulating film for interlayer insulation between the lower structure and the upper structure, removing the natural oxide film formed on the surface of the lower structure; Forming a first insulating film on a surface of the lower structure by a high temperature oxidation process; And forming a second insulating film thicker than the first insulating film by a wet oxidation process on the first insulating film.

본 발명의 제조 방법에 있어서, 상기 제 1 절연막은 800∼900℃ 온도, 0.3∼0.8Torr 반응 챔버내 압력, 10∼30Å의 두께로 형성하며, 상기 제 2 절연막은 800∼900℃ 온도, 0.9∼1.1atm 반응 챔버내 압력, 20∼70Å의 두께로 형성한다.In the manufacturing method of the present invention, the first insulating film is formed at a temperature of 800 to 900 ° C, a pressure in a 0.3 to 0.8 Torr reaction chamber, and a thickness of 10 to 30 kPa, and the second insulating film is a temperature of 800 to 900 ° C and 0.9 to It is formed to a thickness of 20 to 70 kPa under a pressure of 1.1 atm reaction chamber.

상기 목적을 달성하기 위하여 본 발명의 다른 제조 방법은 반도체 기판의 활성 영역과 소자 분리 영역을 정의하는 단계; 상기 기판의 활성 영역 위에 형성된 자연 산화막을 제거하는 단계; 고온 산화 공정을 실시하여 상기 활성 영역 표면에 제 1 절연막을 형성하는 단계; 및 습식 산화 공정으로 상기 제 1 절연막 위에 제 1 절연막보다 두꺼운 제 2 절연막을 형성하는 단계를 포함하여 상기 활성 영역 위에 제 1 절연막 및 제 2 절연막이 적층된 게이트 산화막을 형성하는 것을 특징으로 한다.In order to achieve the above object, another manufacturing method of the present invention comprises the steps of defining an active region and a device isolation region of the semiconductor substrate; Removing the native oxide film formed on the active region of the substrate; Performing a high temperature oxidation process to form a first insulating film on the surface of the active region; And forming a second insulating film thicker than the first insulating film on the first insulating film by a wet oxidation process to form a gate oxide film in which the first insulating film and the second insulating film are stacked on the active region.

본 발명의 제조 방법에 있어서, 상기 제 1 절연막은 800∼900℃ 온도, 0.3∼0.8Torr 반응 챔버내 압력, 10∼30Å의 두께로 형성하며, 상기 제 2 절연막은 800∼900℃ 온도, 0.9∼1.1atm 반응 챔버내 압력, 20∼70Å의 두께로 형성한다.In the manufacturing method of the present invention, the first insulating film is formed at a temperature of 800 to 900 ° C, a pressure in a 0.3 to 0.8 Torr reaction chamber, and a thickness of 10 to 30 kPa, and the second insulating film is a temperature of 800 to 900 ° C and 0.9 to It is formed to a thickness of 20 to 70 kPa under a pressure of 1.1 atm reaction chamber.

본 발명은 게이트 전극 하부의 게이트 산화막 또는 커패시터의 유전막 형성 공정에 적용할 경우 그 두께가 균일하면서 평탄화된 막질을 확보한다.According to the present invention, when applied to the process of forming a dielectric film of a gate oxide film or a capacitor under the gate electrode, the thickness thereof is uniform and the planarized film quality is secured.

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1d는 본 발명의 일 실시예에 따른 반도체 장치의 절연막 형성 공정을 순차적으로 나타낸 공정 순서도이다. 여기서, 절연막은 게이트 산화막을 가르키는 것이다.1A to 1D are process flowcharts sequentially illustrating an insulating film forming process of a semiconductor device according to an embodiment of the present invention. Here, the insulating film indicates a gate oxide film.

본 발명은 도 1a에 나타난 바와 같이 실리콘 기판(10)에 통상의 소자 분리 공정을 실시하여 소자 분리 영역(12)을 형성하여 소자의 활성 영역과 분리 영역을 정의한다. 그리고, 클리닝 공정을 실시하여 기판(10) 표면에 발생된 자연 산화막을 제거하는데, 이 때 사용하는 가스는 H2, NF3, HF 중에서 선택적인 한 가스를 이용한다.In the present invention, as shown in FIG. 1A, a device isolation region 12 is formed by performing a conventional device isolation process on the silicon substrate 10 to define an active region and a isolation region of the device. Then, a cleaning process is performed to remove the natural oxide film generated on the surface of the substrate 10. At this time, a gas selected from H 2 , NF 3 and HF is used.

이어서 웨이퍼를 H2제거(purge) 박스 기능이 있는 LPCVD(Low Press Chemical Vapor Deposition)의 쿼터 보트에 로딩한 후에 H2가스 적당량을 플로우르 비율을 크게 하여 제거 박스 내로 분사시킨다. 일정 시간이 경과된 후 보트를 튜브 내로 로딩하고 상기 결과물에 고온 산화 공정(High Temperature Oxidation)을 실시하여 도 1b에 나타난바와 같이 기판(10) 전면에 제 1 절연막(14)을 형성한다. 이때, 산화 공정의 조건은 800∼900℃의 온도, 0.3∼0.8Torr의 반응 챔버내 압력이며, SiH2Cl2+N2O의 가스를 사용하며, 이 절연막(14)의 두께는 10∼30Å로 한다.Subsequently, the wafer is loaded into a quarter boat of LPCVD (Low Press Chemical Vapor Deposition) with H 2 purge box function, and then an appropriate amount of H 2 gas is injected into the removal box with a large flow ratio. After a certain time has elapsed, the boat is loaded into a tube and the resultant is subjected to a high temperature oxidation process to form a first insulating film 14 on the entire surface of the substrate 10 as shown in FIG. At this time, the condition of the oxidation process is a temperature of 800 to 900 ° C., a pressure in the reaction chamber of 0.3 to 0.8 Torr, and a gas of SiH 2 Cl 2 + N 2 O is used, and the thickness of the insulating film 14 is 10 to 30 kPa. Shall be.

이어서 웨이퍼를 퍼니스에 로딩하여 습식 산화 공정을 실시한다. 이에 도 1C에 나타난 바와 같이 상기 제 1 절연막(14) 위에 제 2 절연막(14')을 성장시킨다. 이때, 산화 공정의 조건은 800∼900℃의 온도, 0.9∼1.1atm의 반응 챔버내 압력이며, 이 절연막(14')의 두께는 20∼70Å로 하여 제 1 절연막(14)보다 더 두껍게 형성한다. 이와 같이 하는 이유는 제 1 절연막(14)을 퍼니스에서 고온으로 산화시켜 막질을 치밀하게 하기 위함이다.The wafer is then loaded into a furnace to perform a wet oxidation process. As shown in FIG. 1C, a second insulating film 14 ′ is grown on the first insulating film 14. At this time, the condition of the oxidation process is a temperature of 800 to 900 占 폚 and a pressure in the reaction chamber of 0.9 to 1.1 atm. The thickness of the insulating film 14 'is 20 to 70 kPa, which is formed thicker than that of the first insulating film 14. . The reason for this is to oxidize the first insulating film 14 at a high temperature in the furnace to make the film quality dense.

이후 도 1d에 나타난 바와 같이 제 2 절연막(14') 위에 화학기상증착공정으로 폴리실리콘을 증착하여 게이트 도전층(16)을 형성한다.Thereafter, as illustrated in FIG. 1D, polysilicon is deposited on the second insulating layer 14 ′ by chemical vapor deposition to form the gate conductive layer 16.

본 발명은 상기와 같은 제 1 절연막(14) 및 제 2 절연막(14')의 형성 공정에 의해 게이트 산화막의 막질을 균일하게 하면서 활성 영역과 산화막 사이의 경계면을 평탄화시킨다.According to the present invention, the interface between the active region and the oxide film is planarized while the film quality of the gate oxide film is made uniform by the process of forming the first insulating film 14 and the second insulating film 14 '.

도 2a 내지 도 2g는 본 발명의 다른 실시예에 따른 반도체 장치의 절연막 형성 공정을 순차적으로 나타낸 공정 순서도이다. 여기서 절연막은 커패시터의 ONO(Oxide Nitride Oxide) 구조의 유전막에 사용되는 산화막을 가르키는 것이다.2A to 2G are process flowcharts sequentially illustrating an insulating film forming process of a semiconductor device according to another exemplary embodiment of the present invention. In this case, the insulating film refers to an oxide film used for a dielectric film of an oxide Nitride Oxide (ONO) structure of a capacitor.

도 2a 내지 도 2g를 참조하면, 본 발명에 따른 커패시터는 다음과 같은 제조 공정에 따라 형성된다.2A to 2G, the capacitor according to the present invention is formed according to the following manufacturing process.

도 2a에 나타난 바와 같이 일련의 공정 순서에 따라 실리콘 기판(10)의 활성 영역에 게이트 산화막(14)을 내재하여 형성된 게이트 전극(16')과 상기 게이트 산화막(14) 에지와 소자 분리 영역(12) 사이의 활성영역 근방에 활성 영역과 다른 도전형 불순물이 주입된 소스/드레인 접합층(18), 하부 소자와 상부 배선의 전기적 절연을 위한 층간 절연막(20), 상기 층간 절연막(20)의 콘택홀을 통해서 소스/드레인 접합층(18)과 접촉되는 금속층으로 이루어진 하부전극(22)을 순차적으로 형성한다.As shown in FIG. 2A, the gate electrode 16 ′ formed by embedding the gate oxide film 14 in the active region of the silicon substrate 10, the edges of the gate oxide film 14, and the device isolation region 12 are formed in the active region of the silicon substrate 10. Source / drain junction layer 18 into which the active region and other conductive impurities are implanted in the vicinity of the active region, the interlayer insulating film 20 for electrical insulation between the lower element and the upper wiring, and the contact between the interlayer insulating film 20 The lower electrode 22 made of a metal layer in contact with the source / drain junction layer 18 is sequentially formed through the hole.

그 다음 도 2b에 나타난 바와 같이 하부 전극이 형성된 결과물 전면에 고온 산화 공정으로 제 1 절연막(24), 예컨대 산화막을 10∼30Å의 두께로 형성한다. 이때 공정 조건은 위에서 설명한 일 실시예와 동일하다.Next, as shown in FIG. 2B, the first insulating film 24, for example, an oxide film is formed to have a thickness of 10 to 30 kPa by the high temperature oxidation process on the entire surface of the resultant in which the lower electrode is formed. In this case, the process conditions are the same as in the above-described embodiment.

그 다음 도 2c에 나타난 바와 같이 습식 산화 공정으로 제 1 절연막(24)을 다시 성장시켜 20∼70Å 두께를 가지는 제 2 절연막(24')인 산화막을 형성한다. 이때 공정 조건은 역시 위에서 설명한 일 실시예와 동일하다.Next, as shown in FIG. 2C, the first insulating film 24 is grown again by a wet oxidation process to form an oxide film, which is the second insulating film 24 ′ having a thickness of 20 to 70 microseconds. In this case, the process conditions are the same as in the above-described embodiment.

그 다음 도 2d에 나타난 바와 같이 제 2 절연막(24') 위에 질화막(26)을 증착하고, 다시 도 2b 내지 도2c와 동일한 공정을 반복 실시한다. 이에 질화막(26)위에는 도 2e 내지 도 2f에 나타난 바와 같이 순차적으로 적층된 절연막(28,28')으로서 산화막들이 형성됨에 따라 ONO 구조의 유전막을 가진다.Next, as illustrated in FIG. 2D, the nitride film 26 is deposited on the second insulating film 24 ′, and the same process as in FIGS. 2B to 2C is repeated. Accordingly, as the oxide films are formed on the nitride film 26 as the insulating films 28 and 28 'sequentially stacked as shown in FIGS. 2E to 2F, the nitride film 26 has a dielectric film having an ONO structure.

이후 ONO 구조의 유전막, 즉 산화막(28') 위에 금속층으로 이루어진 상부전극(30)을 형성한다.Thereafter, an upper electrode 30 made of a metal layer is formed on the dielectric layer of the ONO structure, that is, the oxide layer 28 '.

본 발명은 상기와 같은 제조 공정에 따라 커패시터 유전막에 사용되는 산화막의 막질을 균일한 두께로 형성하면서 산화막과 이에 접촉되는 질화막질간의 경계면을 평탄화시킨다.The present invention flattens the interface between the oxide film and the nitride film in contact therewith while forming the film quality of the oxide film used for the capacitor dielectric film in a uniform thickness according to the above manufacturing process.

본 발명에 의하면, 게이트 전극 하부의 게이트 산화막의 두께를 균일하게 확보하므로써 산화막과 실리콘 기판의 표면 사이를 평탄화하여 전자 이동도에 따른 모스 트랜지스터를 고속화할 수 있다. 또한, 본 발명은 고집적화에 따른 커패시터의 유전 특성을 향상시켜 고정전용량을 확보할 수 있는 효과가 있다.According to the present invention, by uniformly securing the thickness of the gate oxide film under the gate electrode, it is possible to speed up the MOS transistor according to the electron mobility by planarizing between the oxide film and the surface of the silicon substrate. In addition, the present invention has the effect of ensuring a high capacitance by improving the dielectric properties of the capacitor due to high integration.

Claims (3)

커패시터에 절연막을 형성하는 방법에 있어서,In the method of forming an insulating film on a capacitor, 반도체기판에 소정의 하부구조물을 형성한 후, 층간절연막의 콘택홀을 통하여 소스/드레인접합층과 접속되는 금속층으로 이루어진 하부전극을 형성하는 단계와;Forming a lower structure on the semiconductor substrate, and then forming a lower electrode formed of a metal layer connected to the source / drain junction layer through a contact hole of the interlayer insulating film; 상기 결과물 상에 고온 산화 공정을 실시하여 제 1절연막을 형성한 후, 연속하여 상기 결과물에 습식 산화 공정으로 상기 제 1절연막 보다 두꺼운 제 2절연막을 형성하는 단계와;Performing a high temperature oxidation process on the resultant to form a first insulating film, and subsequently forming a second insulating film thicker than the first insulating film by a wet oxidation process on the resultant; 상기 결과물 상에 질화막을 적층하는 단계와;Stacking a nitride film on the resultant product; 상기 질화막 상에 재차 고온 산화 공정으로 제 1절연막을 형성한 후 연속하여 상기 결과물 상에 습식 산화 공정으로 상기 제 1절연막 보다 두꺼운 제 2절연막을 형성하는 단계와;Forming a second insulating film thicker than the first insulating film by a wet oxidation process on the resultant after forming a first insulating film again on the nitride film by a high temperature oxidation process; 상기 결과물 상에 금속층으로 이루어진 상부 전극을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체장치의 절연막 형성방법.And forming an upper electrode formed of a metal layer on the resultant. 제 1 항에 있어서, 상기 제 1 절연막은 800∼900℃ 온도, 0.3∼0.8Torr 반응 챔버내 압력, 10∼30Å의 두께로 형성하는 것을 특징으로 하는 반도체 장치의 절연막 형성 방법.The method of forming an insulating film of a semiconductor device according to claim 1, wherein the first insulating film is formed at a temperature of 800 to 900 占 폚, a pressure in a 0.3 to 0.8 Torr reaction chamber, and a thickness of 10 to 30 kPa. 제 1 항에 있어서, 상기 제 2 절연막은 800∼900℃ 온도, 0.9∼1.1atm 반응 챔버내 압력, 20∼70Å의 두께로 형성하는 것을 특징으로 하는 반도체 장치의 절연막 형성 방법.The method of forming an insulating film of a semiconductor device according to claim 1, wherein the second insulating film is formed at a temperature of 800 to 900 占 폚, a pressure in a 0.9 to 1.1 atm reaction chamber, and a thickness of 20 to 70 Pa.
KR1019970082310A 1997-12-31 1997-12-31 Method for forming isolation layer of semiconductor device KR100292116B1 (en)

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