KR100505452B1 - Capacitor Formation Method of Semiconductor Device - Google Patents

Capacitor Formation Method of Semiconductor Device Download PDF

Info

Publication number
KR100505452B1
KR100505452B1 KR1019970077959A KR19970077959A KR100505452B1 KR 100505452 B1 KR100505452 B1 KR 100505452B1 KR 1019970077959 A KR1019970077959 A KR 1019970077959A KR 19970077959 A KR19970077959 A KR 19970077959A KR 100505452 B1 KR100505452 B1 KR 100505452B1
Authority
KR
South Korea
Prior art keywords
film
forming
capacitor
oxide film
semiconductor device
Prior art date
Application number
KR1019970077959A
Other languages
Korean (ko)
Other versions
KR19990057880A (en
Inventor
김민수
임찬
이길호
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1019970077959A priority Critical patent/KR100505452B1/en
Publication of KR19990057880A publication Critical patent/KR19990057880A/en
Application granted granted Critical
Publication of KR100505452B1 publication Critical patent/KR100505452B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7687—Thin films associated with contacts of capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers

Abstract

본 발명은 유전막으로 산화막-질화막-산화막으로 적층된 절연막을 사용하는 캐패시터 형성 방법에 관한 것으로, 도핑된 폴리실리콘막으로 이루어지는 하부전극과 산화막으로 이루어지는 층간절연막에 질소 이온(N+)을 주입하여, 두 막을 동시에 질화시킴으로써 이후에 증착되는 질화막이 균일한 두께를 갖도록 하며, 산소의 성장 속도를 늦추어 질화막 하부의 산화막을 얇게 형성함으로써 산화막-질화막-산화막으로 적층된 막을 유전막으로 사용하는 캐패시터의 전기용량을 보다 크게 확보하는 방법이다.The present invention relates to a method for forming a capacitor using an insulating film laminated with an oxide film-nitride film-oxide film as a dielectric film, and injecting nitrogen ions (N + ) into an interlayer insulating film made of an oxide film and a lower electrode made of a doped polysilicon film. Nitriding the two films simultaneously ensures that the nitride film deposited thereafter has a uniform thickness, and slows the growth rate of oxygen to form a thin oxide film under the nitride film. It is a way to secure more.

Description

반도체 소자의 캐패시터 형성 방법Capacitor Formation Method of Semiconductor Device

본 발명은 반도체 장치 제조 방법에 관한 것으로 특히, 유전막으로 산화막-질화막-산화막으로 적층된 절연막을 사용하는 캐패시터 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a capacitor using an insulating film laminated by an oxide film-nitride film-oxide film as a dielectric film.

반도체 소자의 고집적화에 따라, 작은 면적에서도 큰 전기용량을 얻을 수 있는 캐패시터 형성이 주요 문제로 대두되고 있다. 캐패시터에 저장되는 전하량(C)은 다음의 식1과 같은 관계가 있다.With the high integration of semiconductor devices, the formation of capacitors capable of obtaining large capacitance even in a small area has emerged as a major problem. The amount of charge C stored in the capacitor has a relation as shown in Equation 1 below.

[식1]

Figure pat00001
[Equation 1]
Figure pat00001

식1에서 ε0는 진공의 유전율, εr는 유전체의 유전율, A는 전하저장전극 표면적, a는 전극간의 간격을 나타낸다.In Equation 1, ε 0 is the dielectric constant of vacuum, ε r is the dielectric constant of dielectric, A is the surface area of charge storage electrode, and a is the distance between electrodes.

최소 선폭이 0.25 ㎛급 이하인 고집적 소자에서는 디자인 룰(design rule)이 급격히 감소함에 따라 캐패시터에 할당된 공간도 감소한다. 따라서, 소자 동작에 충분한 전기용량을 확보하기 위해서는 유전율이 큰 Ta205, (Bi,Sr)TiO3, (Pb, Zr)TiO 등의 고유전 박막을 사용하거나, 전하저장전극의 표면적을 늘리거나 또는 전극간의 간격, 즉 유전막의 두께를 줄여야한다.In the highly integrated device having a minimum line width of 0.25 μm or less, the space allocated to the capacitor also decreases as the design rule sharply decreases. Therefore, in order to secure sufficient capacitance for device operation, high dielectric constant thin films such as Ta 2 O 5 , (Bi, Sr) TiO 3 , (Pb, Zr) TiO, or the like, or increase the surface area of the charge storage electrode Or the gap between the electrodes, i.e. the thickness of the dielectric film, should be reduced.

캐패시터의 유전막으로 사용되는 산화막-질화막-산화막(oxide - nitride -oxide, 이하 ONO막)의 두께를 줄여 전기용량을 확보하는 방법도 있지만, ONO막의 두께를 줄이는데는 한계가 있으며, 유전율이 큰 고유전 박막 등을 사용하여 전기용량을 확보하고자 하는 방법은 아직까지 대량 생산에 적용되고 있지 못한 실정이다.There is also a method of securing the capacitance by reducing the thickness of the oxide-nitride-oxide (ONO film) used as the dielectric film of the capacitor, but there is a limit to reducing the thickness of the ONO film, and has a high dielectric constant The method of securing the capacitance using a thin film or the like has not been applied to mass production yet.

따라서, 선폭이 0.25 ㎛급 이하의 초고집적 소자에서는 3차원 구조의 하부전하저장 전극의 표면에 요철을 주어 전하저장전극의 면적을 증가시키고, 대량 생산에 적합한 ONO막을 유전막으로 형성하는 방법이 이루어지고 있다. 종래에는 ONO막의 형성 방법에서 질화막을 형성하기 전에 HF 용액을 이용한 세정 공정을 실시하여 자연산화막을 제거하고, NH4OH,H2O2 및 H2O가 혼합된 용액을 사용하여 화학적 산화막(Chemical Oxide)을 형성하는데, 이와 같이 형성되는 화학적 산화막의 두께는 7Å 이상이 되어 유전막의 두께를 감소시키는데 어려움이 있다.Therefore, in the ultra-high density device having a line width of 0.25 μm or less, a method of increasing the area of the charge storage electrode by giving irregularities on the surface of the lower charge storage electrode having a three-dimensional structure and forming an ONO film suitable for mass production as a dielectric film is made. have. Conventionally, before forming a nitride film in the method of forming an ONO film, a natural oxide film is removed by performing a cleaning process using a HF solution, and a chemical oxide film is used using a solution in which NH 4 OH, H 2 O 2 and H 2 O are mixed. Oxide) is formed, the thickness of the chemical oxide film formed in this way is more than 7 Å it is difficult to reduce the thickness of the dielectric film.

또한, 산화막 및 폴리실리콘막 상에 질화막을 동시에 형성하면 질화막이 산화막 상에는 SiON의 형태로, 폴리실리콘막 상에는 SixNy의 형태로 증착되어 증착 속도의 차이가 현저하게 나타난다. 유전막의 두께가 50Å 이하가 되도록 캐패시터를 형성하는 공정에서는 산화막 상에서와 폴리실리콘막 상에서의 질화막 증착 속도가 현저하게 차이가 남으로 인하여, 산화막과 폴리실리콘막의 경계에서 질화막 두께의 감소가 심하게 일어나 누설전류가 증가하고 절연파괴가 일어나는 등 소자의 특성을 저하시키는 문제가 발생한다.In addition, when the nitride film is formed on the oxide film and the polysilicon film at the same time, the nitride film is deposited in the form of SiON on the oxide film and in the form of Si x N y on the polysilicon film, so that the difference in deposition rate is remarkable. In the process of forming the capacitor so that the thickness of the dielectric film is 50 kΩ or less, the deposition rate of the nitride film on the oxide film and the polysilicon film is significantly different, so that the thickness of the nitride film is severely reduced at the boundary between the oxide film and the polysilicon film, resulting in leakage current Problem occurs that decreases the device characteristics such as increases and breakdown occurs.

도1은 종래 기술에 따른 캐패시터 형성 방법에서 유전막으로 ONO막을 형성하는 공정 단면도이다. 종래의 캐패시터 유전막 형성 과정에서 ONO막의 질화막을 증착하기 전에 HF와 NH4OH, H2O2 및 H2O를 사용하여 자연산화막을 제거하고, 화학적 산화막을 5 Å 내지 7 Å의 두께로 형성한 후, 질화막(14, 14')을 형성한다. 이때 질화막을 형성하기 전에 산화막으로 이루어지는 층간절연막(11)과 도핑된 폴리실리콘막으로 이루어지는 하부전극(13) 상에 형성되는 질화막의 두께 차이를 완화시키기 위하여, 산화막과 도핑된 폴리실리콘막을 NH3 분위기에서 급속 열처리하거나 또는 질화막 증착로에 NH3 가스를 흘려주며 열처리하여 SiON막을 형성시킨다. 미설명 도면부호 '10' 은 실리콘 기판, '12' 는 폴리실리콘 플러그를 각각 나타낸다.1 is a cross-sectional view of a process of forming an ONO film with a dielectric film in a capacitor forming method according to the prior art. Before depositing the nitride film of the ONO film in the conventional capacitor dielectric film formation process, HF and NH 4 OH, H 2 O 2 and The natural oxide film is removed using H 2 O, and the chemical oxide film is formed to a thickness of 5 GPa to 7 GPa, and then nitride films 14 and 14 'are formed. At this time, in order to alleviate the thickness difference between the interlayer insulating film 11 made of oxide film and the lower electrode 13 made of doped polysilicon film before forming the nitride film, the oxide film and the doped polysilicon film are made into an NH 3 atmosphere. In order to form a SiON film by rapid heat treatment or by heat treatment with flowing NH 3 gas into a nitride film deposition furnace. Reference numeral '10' denotes a silicon substrate, and '12' denotes a polysilicon plug, respectively.

전술한 종래의 캐패시터 형성 방법의 경우 층간절연막(11) 상에는 SiO2에 가까운 SION막(14)이, 도핑된 폴리실리콘막 상에는 Si3N4에 가까운 SION막(14 ')이 형성되기 때문에 두께가 13Å 정도 차이 나게 된다. 이러한 현상은 층간절연막(11)과 하부전극(13)을 이루는 도핑된 폴리실리콘막의 경계에서는 국부적으로 질화막이 얇아지는 현상(A)이 일어나 누설전류 증가 및 절연파괴와 같이 소자 특성을 저하시키는 요인이 된다.In the above-described conventional capacitor formation method, since the SION film 14 close to SiO 2 is formed on the interlayer insulating film 11, and the SION film 14 'close to Si 3 N 4 is formed on the doped polysilicon film, the thickness is reduced. The difference is about 13Å. This phenomenon occurs at the boundary between the doped polysilicon film forming the interlayer insulating film 11 and the lower electrode 13 (A), which causes local thinning of the nitride film (A), which causes deterioration of device characteristics such as increased leakage current and dielectric breakdown. do.

도2는 제1 웨이퍼(W1) 및 제2 웨이퍼(W2)를 HF와 NH4OH, H2O2 및 H2O를 사용하여 세정을 하고 NH3 분위기에서 열처리한 후 제2 웨이퍼(W2) 상에만 1000 Å 두께의 산화막을 형성하고, 제1 및 제2 웨이퍼(W1, W2)에 동일한 조건으로 질화막을 형성한 결과를 나타낸 것이다. 제1 및 제2 웨이퍼(W1, W2) 상에 형성되는 질화막의 두께의 차는 13.5 Å인데, 이 결과로 미루어보아 폴리실리콘막과 산화막 상에 질화막을 동시에 형성할 경우 질화막 두께의 차이는 더 커질 것으로 예상된다.FIG. 2 shows the first wafer W 1 and the second wafer W 2 as HF, NH 4 OH, H 2 O 2, and the like; After heat treating the washed using a H 2 O, and in the NH 3 atmosphere, the second wafer (W 2) onto only an oxide film is formed of a 1000 Å thick, the first and second wafers (W 1, W 2) equal conditions This shows the result of forming the nitride film. The difference in the thickness of the nitride film formed on the first and second wafers W 1 and W 2 is 13.5 Å. As a result, when the nitride film is simultaneously formed on the polysilicon film and the oxide film, the difference in the thickness of the nitride film is further increased. It is expected to grow.

따라서, 산화막과 폴리실리콘막의 경계면에서 질화막이 얇게 형성되는 문제를 해결할 수 있는 공정이 필요하게 되었다.Therefore, there is a need for a process that can solve the problem of forming a thin nitride film at the interface between the oxide film and the polysilicon film.

상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 ONO막을 유전막으로 이용하는 캐패시터 형성 방법에 있어서, 산화막으로 이루어지는 층간절연막 및 도핑된 폴리실리콘막으로 이루어지는 하부전극 상에 균일한 두께의 질화막을 형성할 수 있는 캐패시터 형성 방법을 제공하는데 그 목적이 있다.In order to solve the above problems, the present invention provides a method for forming a capacitor using an ONO film as a dielectric film, wherein a nitride film having a uniform thickness can be formed on an interlayer insulating film made of an oxide film and a lower electrode made of a doped polysilicon film. It is an object of the present invention to provide a method for forming a capacitor.

상기 목적을 달성하기 위한 본 발명은 반도체 기판 상에 형성된 층간절연막을 형성하는 단계; 상기 층간절연막을 선택적으로 식각하여 콘택홀을 형성하는 단계; 상기 콘택홀에 폴리실리콘플러그를 매립하는 단계; 상기 폴리실리콘플러그 상에 도핑된 폴리실리콘막으로 이루어지는 하부전극을 형성하는 단계; 상기 하부전극과 상기 층간절연막에 질소 이온을 주입하는 단계; 상기 질소 이온이 주입된 결과물의 상부에 제1 산화막, 질화막, 제2 산화막을 적층하여 유전막을 형성하는 단계; 및 상기 유전막 상에 상부전극을 형성하는 단계를 포함하여 이루어진다.The present invention for achieving the above object is to form an interlayer insulating film formed on a semiconductor substrate; Selectively etching the interlayer insulating film to form a contact hole; Embedding a polysilicon plug in the contact hole; Forming a lower electrode formed of a doped polysilicon film on the polysilicon plug; Implanting nitrogen ions into the lower electrode and the interlayer dielectric layer; Forming a dielectric film by stacking a first oxide film, a nitride film, and a second oxide film on the resultant in which the nitrogen ions are implanted; And forming an upper electrode on the dielectric layer.

본 발명은 도핑된 폴리실리콘막으로 이루어지는 하부전극과 산화막으로 이루어지는 층간절연막에 질소 이온(N+)을 주입하여, 두 막을 동시에 질화시킴으로써 이후에 증착되는 질화막이 균일한 두께를 갖도록 하고, N+ 이온을 주입하여 산소의 성장 속도를 늦추어 질화막 하부의 산화막을 얇게 형성함으로써 산화막-질화막-산화막으로 적층된 막을 유전막으로 사용하는 캐패시터의 전기용량을 보다 크게 확보하는 방법이다.The present invention injects nitrogen ions (N + ) into a lower electrode made of a doped polysilicon film and an interlayer insulating film made of an oxide film, and simultaneously nitrides both films so that the nitride film deposited thereafter has a uniform thickness, and the N + ions. This method is used to slow the growth rate of oxygen to form a thin oxide film under the nitride film, thereby securing a larger capacitance of a capacitor using the oxide-nitride-oxide film stacked as a dielectric film.

이하, 본 발명의 일실시예에 따른 캐패시터 형성 공정 단면도인 도3을 참조하여 본 발명의 일실시예를 설명한다.Hereinafter, an embodiment of the present invention will be described with reference to FIG. 3, which is a cross-sectional view of a capacitor forming process according to an embodiment of the present invention.

실리콘 기판(20) 상에 형성된 층간절연막(21)을 선택적으로 식각하여 실리콘 기판을 노출하는 콘택홀을 형성한 후 콘택홀 내에 도핑된 폴리실리콘을 매립하여 폴리실리콘 플러그(22)를 형성하고, 도핑된 폴리실리콘막으로 하부전극(23)을 형성한다. 이어서, 도핑된 폴리실리콘막으로 이루어진 하부전극(23) 및 산화막으로 이루어진 층간절연막(22)에 1×1013/㎠ 내지 5×1015/㎠ 양의 N+ 이온을 0.5 keV 내지 10 keV로 주입하고, HF 용액 또는 HF와 NH4F가 혼합된 BOE(buffered oxide etchant) 용액으로 자연산화막을 제거한 후 NH4OH, H2O2 및 H2O 용액을 사용하여 화학적 산화막(도시하지 않음)을 형성한다. 상기 N+ 이온 주입을 실시한 후 NH3 분위기에서 열처리를 실시하기도 한다.By selectively etching the interlayer insulating film 21 formed on the silicon substrate 20 to form a contact hole exposing the silicon substrate, the doped polysilicon is buried in the contact hole to form a polysilicon plug 22, and doped The lower electrode 23 is formed of the polysilicon film. Subsequently, an amount of 1 × 10 13 / cm 2 to 5 × 10 15 / cm 2 of N + ions is implanted at 0.5 keV to 10 keV into the lower electrode 23 made of the doped polysilicon film and the interlayer insulating film 22 made of the oxide film. After removing the natural oxide layer with a HF solution or a BOE (buffered oxide etchant) solution in which HF and NH 4 F are mixed, NH 4 OH, H 2 O 2 and H 2 O solution is used to form a chemical oxide film (not shown). After the N + ion implantation, heat treatment may be performed in an NH 3 atmosphere.

다음으로, 상기 자연산화막 상에 SiH2Cl2 또는 SiH4와 NH3를 혼합한 기체를 이용하여 0.1 Torr 내지 0.5 Torr 압력 및 620 ℃ 내지 750 ℃의 온도 조건으로 30 Å 내지 160 Å 두께의 질화막을 형성하고, 1 기압이 넘지 않는 압력에서 상기 질화막 상에 산화막을 형성한 다음, 산화막 상에 상부전극을 형성하여 캐패시터를 완성한다.Next, a nitride film having a thickness of 30 kPa to 160 kPa is formed on the natural oxide film by using a gas mixed with SiH 2 Cl 2 or SiH 4 and NH 3 at a pressure of 0.1 Torr to 0.5 Torr and a temperature of 620 ° C to 750 ° C. And an oxide film is formed on the nitride film at a pressure not exceeding 1 atm, and then an upper electrode is formed on the oxide film to complete the capacitor.

전술한 바와 같이 층간절연막(22) 및 하부전극(23)에 N+ 이온을 주입함으로써 산화막으로 이루어진 층간절연막(22)과 도핑된 실리콘막으로 이루어진 하부전극(23) 상에 SiN막(24, 24 ')이 형성된다. 즉, N+ 이온을 주입하면 산화막 상에 SiON이 형성되는데, 산화막의 표면상에는 SiN에 가까운 상이 형성되어 결과적으로 도핑된 폴리실리콘막과 산화막 상에 동일하게 SiN 상이 형성되므로, 이후의 질화막 증착공정에서 산화막과 도핑된 폴리실리콘막 상에 증착되는 질화막 두께 차이를 완화시키게 되고, 폴리실리콘막과 산화막의 경계면에도 질화막이 균일한 두께로 형성(B)되어, 유전막의 두께를 50 Å 이하로 형성하는 캐패시터의 누설전류를 감소시키며 절연파괴를 방지할 수 있어 소자의 특성을 향상시키는 것이 가능하다. 또한 N+ 이온을 주입함으로 인하여 산화막의 성장 속도가 늦어져, 이로 인해 질화막 아래의 산화막을 더욱 얇게 형성하는 것이 가능하다.As described above, by injecting N + ions into the interlayer insulating film 22 and the lower electrode 23, the SiN films 24 and 24 are formed on the interlayer insulating film 22 made of an oxide film and the lower electrode 23 made of a doped silicon film. ') Is formed. That is, when N + ions are implanted, SiON is formed on the oxide film, and a phase close to SiN is formed on the surface of the oxide film. As a result, a SiN phase is formed on the doped polysilicon film and the oxide film. Capacitors to alleviate the difference in the thickness of the nitride film deposited on the oxide film and the doped polysilicon film, and the nitride film is formed to have a uniform thickness on the interface between the polysilicon film and the oxide film (B), thereby forming a dielectric film thickness of 50 Å or less It is possible to improve the characteristics of the device by reducing leakage current and preventing insulation breakdown. In addition, the growth rate of the oxide film is slowed by the implantation of N + ions, which makes it possible to form a thinner oxide film under the nitride film.

전술한 본 발명의 일실시예에서는 N+ 이온을 주입한 후 HF 용액으로 자연산화막을 제거하고, NH4OH, H2O2 및 H2O 용액을 사용하여 화학적 산화막을 형성하는 것을 설명하였지만, HF 용액으로 자연산화막을 형성한 후에 실시하는 화학적 산화막을 형성 과정은 생략이 가능하다. 즉, 질화막을 형성하기 위한 튜브(tube)에 웨이퍼를 인입(loading) 하는 동안에 웨이퍼 상에 자라나는 3 Å 이하 두께의 자연산화막을 질화막 하부의 산화막으로 대신하게 된다.In the above-described embodiment of the present invention, after implanting N + ions, the natural oxide film is removed with HF solution, and NH 4 OH, H 2 O 2 and Although the chemical oxide film is formed using the H 2 O solution, the process of forming the chemical oxide film after the natural oxide film is formed with the HF solution can be omitted. That is, during loading of the wafer into the tube for forming the nitride film, a native oxide film having a thickness of 3 Å or less that grows on the wafer is replaced by the oxide film under the nitride film.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the technical field of the present invention without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

상기와 같이 이루어지는 본 발명은 질화막을 증착하기 전에 산화막으로 이루어지는 층간절연막 및 도핑된 폴리실리콘막으로 이루어지는 하부전극에 N+ 이온을 주입하여 산화막과 도핑된 폴리실리콘막 상에 SiN막을 형성함으로써, 산화막과 도핑된 폴리실리콘막 상에 증착되는 질화막의 두께 차이를 완화시켜 두께가 50 Å이 넘지 않는 캐패시터의 누설전류 및 절연파괴에 의한 소자 특성 저하를 방지할 수 있다. 또한, N+ 이온 주입하여 산화막의 성장 속도를 늦추어 질화막 하부의 산화막을 보다 얇게 형성하는 것이 가능하여 ONO막을 유전막으로 사용하는 캐패시터의 전기용량을 보다 증가시키는 것이 가능하다.The present invention made as described above forms an SiN film on an oxide film and a doped polysilicon film by injecting N + ions into an interlayer insulating film made of an oxide film and a lower electrode made of a doped polysilicon film before depositing a nitride film. By reducing the thickness difference of the nitride film deposited on the doped polysilicon film, it is possible to prevent deterioration of device characteristics due to leakage current and dielectric breakdown of a capacitor having a thickness not exceeding 50 mA. In addition, it is possible to form a thinner oxide film under the nitride film by slowing the growth rate of the oxide film by implanting N + ions, thereby increasing the capacitance of the capacitor using the ONO film as the dielectric film.

도1은 종래 기술에 따른 캐패시터 형성 공정 단면도1 is a cross-sectional view of a capacitor forming process according to the prior art

도2는 산화막 형성으로 인한 질화막 형성 두께의 변화를 보이는 그래프2 is a graph showing a change in nitride film formation thickness due to oxide film formation

도3은 본 발명의 일실시예에 따른 캐패시터 형성 공정 단면도Figure 3 is a cross-sectional view of the capacitor formation process according to an embodiment of the present invention

* 도면의 주요 부분에 대한 설명* Description of the main parts of the drawing

20: 실리콘 기판 21: 층간절연막20: silicon substrate 21: interlayer insulating film

22: 폴리실리콘 플러그 23: 하부전극22: polysilicon plug 23: lower electrode

24, 24 ': SiN막24, 24 ': SiN film

Claims (13)

반도체 기판 상에 형성된 층간절연막을 형성하는 단계;Forming an interlayer insulating film formed on the semiconductor substrate; 상기 층간절연막을 선택적으로 식각하여 콘택홀을 형성하는 단계;Selectively etching the interlayer insulating film to form a contact hole; 상기 콘택홀에 폴리실리콘플러그를 매립하는 단계;Embedding a polysilicon plug in the contact hole; 상기 폴리실리콘플러그 상에 도핑된 폴리실리콘막으로 이루어지는 하부전극을 형성하는 단계;Forming a lower electrode formed of a doped polysilicon film on the polysilicon plug; 상기 하부전극과 상기 층간절연막에 질소 이온을 주입하는 단계;Implanting nitrogen ions into the lower electrode and the interlayer dielectric layer; 상기 질소 이온이 주입된 결과물의 상부에 제1 산화막, 질화막, 제2 산화막을 적층하여 유전막을 형성하는 단계; 및Forming a dielectric film by stacking a first oxide film, a nitride film, and a second oxide film on the resultant in which the nitrogen ions are implanted; And 상기 유전막 상에 상부전극을 형성하는 단계Forming an upper electrode on the dielectric layer 를 포함하는 반도체소자의 캐패시터 제조 방법.Capacitor manufacturing method of a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 질소 이온은,The nitrogen ion is, 1×1013/㎠ 내지 5×1015/㎠의 농도로 주입하는 반도체 소자의 캐패시터 형성 방법.A method for forming a capacitor of a semiconductor device to be injected at a concentration of 1 × 10 13 / cm 2 to 5 × 10 15 / cm 2. 제 2 항에 있어서,The method of claim 2, 상기 질소 이온은,The nitrogen ion is, 0.5 keV 내지 10 keV의 에너지로 주입하는 반도체 소자의 캐패시터 형성 방법.Method for forming a capacitor of a semiconductor device implanted with energy of 0.5 keV to 10 keV. 제 1 항에 있어서,The method of claim 1, 상기 질소 이온을 주입하는 단계 후,After implanting the nitrogen ions, 자연산화막을 제거하는 단계를 더 포함하는 반도체 소자의 캐패시터 형성 방법.Capacitor forming method of a semiconductor device further comprising the step of removing the native oxide film. 제 4 항에 있어서,The method of claim 4, wherein 상기 자연산화막 제거는,The natural oxide film is removed, HF 용액 또는 HF와 NH4F가 혼합된 BOE(Buffered oxide etchant) 용액을 사용하는 반도체 소자의 캐패시터 형성 방법.A method of forming a capacitor in a semiconductor device using an HF solution or a buffered oxide etchant (BOE) solution in which HF and NH 4 F are mixed. 제 4 항에 있어서,The method of claim 4, wherein 상기 자연산화막을 제거하는 단계 후,After removing the natural oxide film, 상기 제1 산화막으로 화학적 산화막을 형성하는 반도체 소자의 캐패시터 형성 방법.And forming a chemical oxide film from the first oxide film. 제 6 항에 있어서,The method of claim 6, 상기 제1 산화막은,The first oxide film, NH4OH, H2O2 및 H2O가 혼합된 용액을 이용하여 형성하는 반도체 소자의 캐패시터 형성 방법.A method for forming a capacitor of a semiconductor device, which is formed using a solution in which NH 4 OH, H 2 O 2, and H 2 O are mixed. 제 1 항에 있어서,The method of claim 1, 상기 질소 이온을 주입하는 단계 후,After implanting the nitrogen ions, NH3 분위기에서 열처리하는 단계를 더 포함하는 반도체 소자의 캐패시터 형성 방법.The method of forming a capacitor of a semiconductor device further comprising the step of heat treatment in an NH 3 atmosphere. 제 1 항에 있어서,The method of claim 1, 상기 질화막은,The nitride film, SiH2Cl2 또는 SiH4와 NH3를 혼합한 기체를 이용하여 형성하는 반도체 소자의 캐패시터 형성 방법.A method for forming a capacitor of a semiconductor device, which is formed using a mixture of SiH 2 Cl 2 or SiH 4 and NH 3 . 제 9 항에 있어서,The method of claim 9, 상기 질화막은,The nitride film, 0.1 Torr 내지 0.5 Torr 압력에서 형성하는 반도체 소자의 캐패시터 형성 방법.A method for forming a capacitor of a semiconductor device formed at a pressure of 0.1 Torr to 0.5 Torr. 제 10 항에 있어서,The method of claim 10, 상기 질화막은,The nitride film, 620 ℃ 내지 750 ℃에서 형성하는 반도체 소자의 캐패시터 형성 방법.A method for forming a capacitor of a semiconductor device formed at 620 ℃ to 750 ℃. 제 9 항에 있어서,The method of claim 9, 상기 질화막은,The nitride film, 30 Å 내지 160 Å으로 형성하는 반도체 소자의 캐패시터 형성 방법.A method for forming a capacitor of a semiconductor device, which is formed from 30 Hz to 160 Hz. 제 1 항에 있어서,The method of claim 1, 상기 제2 산화막은,The second oxide film, 1 기압이 넘지 않는 압력에서 형성하는 반도체 소자의 캐패시터 형성 방법.A method for forming a capacitor of a semiconductor device, which is formed at a pressure not exceeding 1 atmosphere.
KR1019970077959A 1997-12-30 1997-12-30 Capacitor Formation Method of Semiconductor Device KR100505452B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019970077959A KR100505452B1 (en) 1997-12-30 1997-12-30 Capacitor Formation Method of Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970077959A KR100505452B1 (en) 1997-12-30 1997-12-30 Capacitor Formation Method of Semiconductor Device

Publications (2)

Publication Number Publication Date
KR19990057880A KR19990057880A (en) 1999-07-15
KR100505452B1 true KR100505452B1 (en) 2005-10-14

Family

ID=37305383

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970077959A KR100505452B1 (en) 1997-12-30 1997-12-30 Capacitor Formation Method of Semiconductor Device

Country Status (1)

Country Link
KR (1) KR100505452B1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950030336A (en) * 1994-04-22 1995-11-24 김주용 Method of forming dielectric film of capacitor
KR960019718A (en) * 1994-11-11 1996-06-17 김주용 Capacitor Structure and Manufacturing Method Thereof
KR960039188A (en) * 1995-04-04 1996-11-21 김주영 Method of forming dielectric film of semiconductor device
KR970018593A (en) * 1995-09-29 1997-04-30 김광호 Method of manufacturing semiconductor device with plasma ammonia treatment
KR0131062B1 (en) * 1992-08-27 1998-04-14 순페이 야마자끼 Fabrication method for film-like semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0131062B1 (en) * 1992-08-27 1998-04-14 순페이 야마자끼 Fabrication method for film-like semiconductor device
KR950030336A (en) * 1994-04-22 1995-11-24 김주용 Method of forming dielectric film of capacitor
KR960019718A (en) * 1994-11-11 1996-06-17 김주용 Capacitor Structure and Manufacturing Method Thereof
KR960039188A (en) * 1995-04-04 1996-11-21 김주영 Method of forming dielectric film of semiconductor device
KR970018593A (en) * 1995-09-29 1997-04-30 김광호 Method of manufacturing semiconductor device with plasma ammonia treatment
KR100292402B1 (en) * 1995-09-29 2001-09-17 윤종용 Method for manufacturing semiconductor device having plasma ammonium process

Also Published As

Publication number Publication date
KR19990057880A (en) 1999-07-15

Similar Documents

Publication Publication Date Title
US6177696B1 (en) Integration scheme enhancing deep trench capacitance in semiconductor integrated circuit devices
US5786248A (en) Semiconductor processing method of forming a tantalum oxide containing capacitor
US5989973A (en) Semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon and a hemispherical grain polysilicon layer produced according to the method
KR100207444B1 (en) Capacitor fabrication method and its device having high dielectronic layer and electrode
KR100401503B1 (en) Method for fabricating capacitor of semiconductor device
US6704188B2 (en) Ultra thin TCS (SiCL4) cell nitride for dram capacitor with DCS (SiH2Cl2) interface seeding layer
KR100596832B1 (en) Method and apparatus for minimizing diffusion in stacked capacitors formed on silicon plugs
US20020102808A1 (en) Method for raising capacitance of a trench capacitor and reducing leakage current
US7153739B2 (en) Method for manufacturing a capacitor of a semiconductor device
KR100505452B1 (en) Capacitor Formation Method of Semiconductor Device
US6080623A (en) Method of manufacturing capacitive element with a non-doped semiconductor film to minimize native oxide formation
KR100480914B1 (en) Method for fabricating semiconductor device
KR100318456B1 (en) A method for forming tantalum oxide capacitor in semiconductor device
KR100492901B1 (en) Manufacturing Method of Dielectric Capacitor of Semiconductor Device
US20040126964A1 (en) Method for fabricating capacitor in semiconductor device
KR100315018B1 (en) Method for forming charge storage electrode of DRAM device
KR20000039607A (en) Method for fabricating capacitor of semiconductor device
KR100187655B1 (en) Capacitor fabrication method of semiconductor device
KR100351449B1 (en) Method For Forming The Gate Electrode Of Semiconductor Device
KR100292116B1 (en) Method for forming isolation layer of semiconductor device
KR100875648B1 (en) Capacitor Manufacturing Method of Semiconductor Device
KR100235973B1 (en) Manufacturing method of capacitor in the semiconductor device
KR100265345B1 (en) Method for fabricating high dielectric capacitor of semiconductor device
KR100363698B1 (en) Method For Forming The Charge Storage Node Of Capacitor
KR950005267B1 (en) Semiconductor device having dielectric layer and manufacturing method thereof

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20100624

Year of fee payment: 6

LAPS Lapse due to unpaid annual fee